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latticexp family data sheet ds1001 version 05.1, november 2007
july 2007 data sheet ds1001 ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 1-1 ds1001 introduction_01.5a july 6, 2007 3:01 p.m. features non-volatile, in?itely recon?urable instant-on ?powers up in microseconds no external con?uration memory excellent design security, no bit stream to intercept recon?ure sram based logic in milliseconds sram and non-volatile memory programmable through system con?uration and jtag ports sleep mode allows up to 1000x static current reduction transfr recon?uration (tfr) in-?ld logic update while system operates extensive density and package options 3.1k to 19.7k lut4s 62 to 340 i/os density migration supported embedded and distributed memory 54 kbits to 396 kbits sysmem embedded block ram up to 79 kbits distributed ram flexible memory resources: ? distributed and block memory flexible i/o buffer programmable sysio buffer supports wide range of interfaces: ? lvcmos 3.3/2.5/1.8/1.5/1.2 ? lvttl sstl 18 class i ? sstl 3/2 class i, ii hstl15 class i, iii ? hstl 18 class i, ii, iii ? pci ? lvds, bus-lvds, lvpecl, rsds dedicated ddr memory support implements interface up to ddr333 (166mhz) sysclock plls up to 4 analog plls per device clock multiply, divide and phase shifting system level support ieee standard 1149.1 boundary scan, plus isptracy internal logic analyzer capability onboard oscillator for con?uration devices operate with 3.3v, 2.5v, 1.8v or 1.2v power supply table 1-1. latticexp family selection guide device lfxp3 lfxp6 lfxp10 LFXP15 lfxp20 pfu/pff rows 16 24 32 40 44 pfu/pff columns 24 30 38 48 56 pfu/pff (total) 384 720 1216 1932 2464 luts (k) 3 6 10 15 20 distributed ram (kbits) 12 23 39 61 79 ebr sram (kbits) 54 72 216 324 396 ebr sram blocks 6 8 24 36 44 v cc voltage 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v 1.2/1.8/2.5/3.3v plls 22444 max. i/o 136 188 244 300 340 packages and i/o combinations: 100-pin tqfp (14 x 14 mm) 62 144-pin tqfp (20 x 20 mm) 100 100 208-pin pqfp (28 x 28 mm) 136 142 256-ball fpbga (17 x 17 mm) 188 188 188 188 388-ball fpbga (23 x 23 mm) 244 268 268 484-ball fpbga (23 x 23 mm) 300 340 latticexp family data sheet introduction
introduction lattice semiconductor latticexp family data sheet 1-2 introduction the latticexp family of fpga devices combine logic gates, embedded memory and high performance i/os in a single architecture that is both non-volatile and in?itely recon?urable to support cost-effective system designs. the re-programmable non-volatile technology used in the latticexp family is the next generation ispxp technol- ogy. with this technology, expensive external con?uration memories are not required and designs are secured from unauthorized read-back. in addition, instant-on capability allows for easy interfacing in many applications. the isplever design tool from lattice allows large complex designs to be ef?iently implemented using the lat- ticexp family of fpga devices. synthesis library support for latticexp is available for popular logic synthesis tools. the isplever tool uses the synthesis tool output along with the constraints from its ?or planning tools to place and route the design in the latticexp device. the isplever tool extracts the timing from the routing and back- annotates it into the design for timing veri?ation. lattice provides many pre-designed ip (intellectual property) isplevercore modules for the latticexp family. by using these ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
july 2007 data sheet ds1001 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 2-1 ds1001 architecture_02.0 july 6, 2007 3:03 p.m. architecture overview the latticexp architecture contains an array of logic blocks surrounded by programmable i/o cells (pic). inter- spersed between the rows of logic blocks are rows of sysmem embedded block ram (ebr) as shown in figure 2- 1. on the left and right sides of the pfu array, there are non-volatile memory blocks. in con?uration mode this non- volatile memory is programmed via the ieee 1149.1 tap port or the sysconfig peripheral port. on power up, the con?uration data is transferred from the non-volatile memory blocks to the con?uration sram. with this technology, expensive external con?uration memories are not required and designs are secured from unautho- rized read-back. this transfer of data from non-volatile memory to con?uration sram via wide busses happens in microseconds, providing an ?nstant-on capability that allows easy interfacing in many applications. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram/rom (pff). the pfu contains the building blocks for logic, arithmetic, ram, rom and register func- tions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for ?xibility, allowing complex designs to be implemented quickly and ef?iently. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. the pfu blocks are used on the out- side rows. the rest of the core consists of rows of pff blocks interspersed with rows of pfu blocks. for every three rows of pff blocks there is a row of pfu blocks. each pic block encompasses two pios (pio pairs) with their respective sysio interfaces. pio pairs on the left and right edges of the device can be con?ured as lvds transmit/receive pairs. sysmem ebrs are large dedicated fast memory blocks. they can be con?ured as ram or rom. the pfu, pff, pic and ebr blocks are arranged in a two-dimensional grid with rows and columns as shown in figure 2-1. the blocks are connected with many vertical and horizontal routing channel resources. the place and route software tool automatically allocates these routing resources. at the end of the rows containing the sysmem blocks are the sysclock phase locked loop (pll) blocks. these plls have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. the latticexp architecture provides up to four plls per device. every device in the family has a jtag port with internal logic analyzer (isptracy) capability. the sysconfig port which allows for serial or parallel device con?uration. the latticexp devices are available for operation from 3.3v, 2.5v, 1.8v and 1.2v power supplies, providing easy integration into the overall system. latticexp family data sheet architecture
2-2 architecture lattice semiconductor latticexp family data sheet figure 2-1. latticexp top level block diagram pfu and pff blocks the core of the latticexp devices consists of pfu and pff blocks. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remainder of the data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered 0-3 as shown in figure 2-2. all the interconnec- tions to and from pfu blocks are from routing. there are 53 inputs and 25 outputs associated with each pfu block. figure 2-2. pfu diagram programmable i/o cell (pic) includes sysio interface non-volatile memory sysconfig programming port (includes dedicated and dual use pins) programmable functional unit (pfu) sysclock pll pff (pfu without ram) jtag port sysmem embedded block ram (ebr) slice 0 lut4 & carry lut4 & carry ff/ latch d ff/ latch d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 & carry lut4 & carry ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d
2-3 architecture lattice semiconductor latticexp family data sheet slice each slice contains two lut4 lookup tables feeding two registers (programmed to be in ff or latch mode), and some associated logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-3 shows an overview of the internal logic of the slice. the registers in the slice can be con?ured for positive/negative and edge/level clocks. there are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or pfu). there are 7 outputs: 6 to routing and one to carry-chain (to adjacent pfu). table 2-1 lists the signals associated with each slice. figure 2-3. slice diagram lut4 & carry lut4 & carry slice a0 b0 c0 d0 ff/ latch ofx0 f0 q0 a1 b1 c1 d1 ci ci co co f sum ce clk lsr ff/ latch ofx1 f1 q1 f sum d d m1 to / from different slice / pfu fast carry out (fco) to / from different slice / pfu fast carry in (fci) lut expansion mux m0 ofx0 from routing to routing control signals selected and inverted per slice in routing note: some interslice signals are not shown.
2-4 architecture lattice semiconductor latticexp family data sheet table 2-1. slice signal descriptions modes of operation each slice is capable of four modes of operation: logic, ripple, ram and rom. the slice in the pff is capable of all modes except ram. table 2-2 lists the modes and the capability of the slice blocks. table 2-2. slice modes logic mode: in this mode, the luts in each slice are con?ured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any logic function with four inputs can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger lookup tables such as lut6, lut7 and lut8 can be constructed by concatenating other slices. ripple mode: ripple mode allows the ef?ient implementation of small arithmetic functions. in ripple mode, the fol- lowing functions can be implemented by each slice: addition 2-bit subtraction 2-bit add/subtract 2-bit using dynamic control up counter 2-bit down counter 2-bit ripple mode multiplier building block comparator functions of a and b inputs - a greater-than-or-equal-to b - a not-equal-to b - a less-than-or-equal-to b two additional signals: carry generate and carry propagate are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. ram mode: in this mode, distributed ram can be constructed using each lut block as a 16x1-bit memory. through the combination of luts and slices, a variety of different memories can be constructed. function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fcin fast carry in 1 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco for the right most pfu the fast carry chain output 1 1. see figure 2-2 for connection details. 2. requires two pfus. logic ripple ram rom pfu slice lut 4x2 or lut 5x1 2-bit arithmetic unit sp 16x2 rom 16x1 x 2 pff slice lut 4x2 or lut 5x1 2-bit arithmetic unit n/a rom 16x1 x 2
2-5 architecture lattice semiconductor latticexp family data sheet the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. figure 2-4 shows the dis- tributed memory primitive block diagrams. dual port memories involve the pairing of two slices, one slice functions as the read-write port. the other companion slice supports the read-only port. for more information on ram mode in latticexp devices, please see details of additional technical documentation at the end of this data sheet. table 2-3. number of slices required for implementing distributed ram figure 2-4. distributed memory primitives rom mode: the rom mode uses the same principal as the ram modes, but without the write port. pre-loading is accomplished through the programming interface during con?uration. pfu modes of operation slices can be combined within a pfu to form larger functions. table 2-4 tabulates these modes and documents the functionality possible at the pfu level. spr16x2 dpr16x2 number of slices 1 2 note: spr = single port ram, dpr = dual port ram do1 do0 di0 di1 ad0 ad1 ad2 ad3 wre ck do0 ad0 ad1 ad2 ad3 dpr16x2 spr16x2 rom16x1 rdo1 rdo0 di0 di1 wck wre wdo1 wdo0 wad0 wad1 wad2 wad3 rad0 rad1 rad2 rad3
2-6 architecture lattice semiconductor latticexp family data sheet table 2-4. pfu modes of operation routing there are many resources provided in the latticexp devices to route signals individually or as buses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) and x6 (spans seven pfu). the x1 and x2 connections provide fast and ef?ient connections in horizontal, vertical and diagonal directions. the x2 and x6 resources are buffered allowing both short and long connections routing between pfus. the isplever design tool takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. clock distribution network the clock inputs are selected from external i/o, the sysclock plls or routing. these clock inputs are fed through the chip via a clock distribution system. primary clock sources latticexp devices derive clocks from three primary sources: pll outputs, dedicated clock inputs and routing. lat- ticexp devices have two to four sysclock plls, located on the left and right sides of the device. there are four dedicated clock inputs, one on each side of the device. figure 2-5 shows the 20 primary clock sources. logic ripple ram 1 rom lut 4x8 or mux 2x1 x 8 2-bit add x 4 spr16x2 x 4 dpr16x2 x 2 rom16x1 x 8 lut 5x4 or mux 4x1 x 4 2-bit sub x 4 spr16x4 x 2 dpr16x4 x 1 rom16x2 x 4 lut 6x 2 or mux 8x1 x 2 2-bit counter x 4 spr16x8 x 1 rom16x4 x 2 lut 7x1 or mux 16x1 x 1 2-bit comp x 4 rom16x8 x 1 1. these modes are not available in pff blocks
2-7 architecture lattice semiconductor latticexp family data sheet figure 2-5. primary clock sources secondary clock sources latticexp devices have four secondary clock resources per quadrant. the secondary clock branches are tapped at every pfu. these secondary clock networks can also be used for controls and high fanout data. these secondary clocks are derived from four clock input pads and 16 routing signals as shown in figure 2-6. from routing clock input from routing pll input clock input pll input pll input clock input pll input from routing clock input from routing pll pll pll pll 20 primary clock sources to quadrant clock selection note: smaller devices have two plls.
2-8 architecture lattice semiconductor latticexp family data sheet figure 2-6. secondary clock sources clock routing the clock routing structure in latticexp devices consists of four primary clock lines and a secondary clock net- work per quadrant. the primary clocks are generated from muxs located in each quadrant. figure 2-7 shows this clock routing. the four secondary clocks are generated from muxs located in each quadrant as shown in figure 2- 8. each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in figure 2- 9. figure 2-7. per quadrant primary clock selection 20 secondary clock sources to quadrant clock selection from routing from routing clock input clock input from routing from routing from routing from routing from routing from routing from routing from routing from routing clock input clock input from routing from routing from routing from routing from routing 4 primary clocks (clk0, clk1, clk2, clk3) per quadrant 20 primary clock sources: 12 plls + 4 pios + 4 routing 1 dcs 2 dcs 2 1. smaller devices have fewer pll related lines. 2. dynamic clock select.
2-9 architecture lattice semiconductor latticexp family data sheet figure 2-8. per quadrant secondary clock selection figure 2-9. slice clock selection sysclock phase locked loops (plls) the pll clock input, from pin or routing, feeds into an input clock divider. there are three sources of feedback sig- nals to the feedback divider: from clkop (pll internal), from clock net (clkop or clkos) or from a user clock (pin or logic). there is a pll_lock signal to indicate that vco has locked on to the input clock signal. figure 2-10 shows the sysclock pll diagram. the setup and hold times of the device can be improved by programming a delay in the feedback or input path of the pll which will advance or delay the output clock with reference to the input clock. this delay can be either pro- grammed during con?uration or can be adjusted dynamically. in dynamic mode, the pll may lose lock after adjustment and not relock until the t lock parameter has been satis?d. additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the clkos output. the sysclock plls provide the ability to synthesize clock frequencies. each pll has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. the input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. the post scalar divider allows the vco to operate at higher frequencies than the clock output, thereby increasing the fre- quency range. the secondary divider is used to derive lower frequency outputs. 4 secondary clocks per quadrant 20 secondary clock feedlines : 4 clock input pads + 16 routing signals primary clock secondary clock routing clock to each slice gnd
2-10 architecture lattice semiconductor latticexp family data sheet figure 2-10. pll diagram figure 2-11 shows the available macros for the pll. table 2-11 provides signal description of the pll block. figure 2-11. pll primitive table 2-5. pll signal descriptions signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) rst i ? to reset input clock divider clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ? indicates pll lock to clki ddamode i dynamic delay enable. ? pin control (dynamic), ?? fuse control (static) ddaizr i dynamic delay zero. ?? delay = 0, ?? delay = on ddailag i dynamic delay lag/lead. ?? lag, ?? lead ddaidel[2:0] i dynamic delay input ddaozr o dynamic delay zero output ddaolag o dynamic delay lag/lead output ddaodel[2:0] o dynamic delay output vco clkos clkok lock rst clkfb from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) dynamic delay adjustment input clock divider (clki) feedback divider (clkfb) post scalar divider (clkop) phase/duty select secondary clock divider (clkok) delay adjust voltage controlled oscillator clki (from routing or external pin) clkop epllb clkop clki clkfb lock ehxpllb clkos clki clkfb clkok lock rst clkop ddaizr ddailag dda mode ddaidel[2:0] ddaozr ddaolag ddaodel[2:0]
2-11 architecture lattice semiconductor latticexp family data sheet for more information on the pll, please see details of additional technical documentation at the end of this data sheet. dynamic clock select (dcs) the dcs is a global clock buffer with smart multiplexer functions. it takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. this is achieved irrespective of where the select signal is toggled. there are eight dcs blocks per device, located in pairs at the center of each side. figure 2-12 illustrates the dcs block macro. figure 2-12. dcs block primitive figure 2-13 shows timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information on the dcs, please see details of additional technical documentation at the end of this data sheet. figure 2-13. dcs waveforms sysmem memory the latticexp family of devices contain a number of sysmem embedded block ram (ebr). the ebr consists of a 9-kbit ram, with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-6. dcs clk0 dcsout clk1 sel clk0 sel dcsout clk1
2-12 architecture lattice semiconductor latticexp family data sheet table 2-6. sysmem block con?urations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1 and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device con?uration. by preloading the ram block during the chip con?uration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of rams can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci? design inputs. single, dual and pseudo-dual port modes figure 2-14 shows the four basic memory con?urations and their input/output names. in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. memory mode con?urations single port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 true dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 pseudo dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36
2-13 architecture lattice semiconductor latticexp family data sheet figure 2-14. sysmem memory primitives the ebr memory supports three forms of write behavior for single port or dual port operation: 1. normal ?data on the output appears only during read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. write through - a copy of the input data appears at the output of the same port during a write cycle. this mode is supported for all data widths. 3. read-before-write ?when new data is being written, the old content of the address appears at the output. this mode is supported for x9, x18 and x36 data widths. memory core reset the memory array in the ebr utilizes latches at the a and b output ports. these latches can be reset asynchro- nously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respec- tively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-15. ebr ad[12:0] di[35:0] clk ce rst we cs[2:0] do[35:0] single port ram ebr true dual port ram pseudo-dual port ram rom ad[12:0] clk ce do[35:0] rst cs[2:0] ebr ebr ada[12:0] dia[17:0] clka cea rsta wea csa[2:0] doa[17:0] adb[12:0] dib[17:0] clkb ceb rstb web csb[2:0] dob[17:0] adw[12:0] di[35:0] clkw cew adr[12:0] do[35:0] cer clkr we rst cs[2:0]
2-14 architecture lattice semiconductor latticexp family data sheet figure 2-15. memory core reset for further information on sysmem ebr block, see the details of additional technical documentation at the end of this data sheet. ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in figure 2-16. the gsr input to the ebr is always asynchronous. figure 2-16. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. if an ebr is pre-loaded during con?uration, the gsr input must be disabled or the release of the gsr during device wake up must occur before the release of the device i/os becoming active. these instructions apply to all ebr ram and rom implementations. note that there are no reset restrictions if the ebr synchronous reset is used and the ebr gsr input is disabled. programmable i/o cells (pics) each pic contains two pios connected to their respective sysio buffers which are then connected to the pads as shown in figure 2-17. the pio block supplies the output data (do) and the tri-state control signal (to) to sysio buffer, and receives input from the buffer. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn programmable disable rsta l clr reset clock clock ena b le
2-15 architecture lattice semiconductor latticexp family data sheet figure 2-17. pic diagram in the latticexp family, seven pios or four (3.5) pics are grouped together to provide two lvds differential pairs, one pic pair and one single i/o, as shown in figure 2-18. two adjacent pios can be joined to provide a differential i/o pair (labeled as ? and ??. the pad labels ? and ? distinguish the two pios. only the pio pairs on the left and right edges of the device can be con?ured as lvds transmit/receive pairs. one of every 14 pios (a group of 8 pics) contains a delay element to facilitate the generation of dqs signals as shown in figure 2-19. the dqs signal feeds the dqs bus which spans the set of 13 pios (8 pics). the dqs sig- nal from the bus is used to strobe the ddr data from the memory into input register blocks. this interface is designed for memories that support one dqs strobe per eight bits of data. the exact dqs pins are shown in a dual function in the logic signal connections table in this data sheet. addi- tional detail is provided in the signal descriptions table in this data sheet. pio b pa da "t" padb ? opos0 oneg0 opos1 oneg1 td inck indd inff ipos0 ipos1 clk ce lsr gsrn clko clki ceo cei pio a sysio buffer control muxes lsr gsr dqs ddrclkpol iold0 iolt0 d0 ddrclk di ipos1 ipos0 inck indd inff d0 d1 td d1 do tristate register block (2 flip flops) output register block (2 flip flops) ddrclk input register block (5 flip flops)
2-16 architecture lattice semiconductor latticexp family data sheet figure 2-18. group of seven pios figure 2-19. dqs routing pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic block. these blocks contain registers for both single data rate (sdr) and double data rate (ddr) operation along with the necessary clock and selection logic. programmable delay lines used to shift incoming clock and data sig- nals are also included in these blocks. input register block the input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. figure 2-20 shows the diagram of the input register block. input signals are fed from the sysio buffer to the input register block (as signal di). if desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and pio a pio b pio a pio b pio a pio a pio b pada ? padb ? lvds pair pada ? padb ? pada ? padb ? lvds pair pada ? four pics one pio pair pio a pio b pada ? padb ? pio b pio a assigned dqs pin dqs sysio buffer lvds pair lvds pair pio a pio b pada ? padb ? pio a pio b pada ? padb ? lvds pair pio a pada ? pio b pada ? padb ? padb ? pio a pio b pada ? padb ? pio a pio b pada ? padb ? lvds pair delay
2-17 architecture lattice semiconductor latticexp family data sheet in selected blocks the input to the dqs delay block. if one of the bypass options is not chosen, the signal ?st passes through an optional delay block. this delay, if selected, ensures no positive input-register hold-time require- ment when using a global clock. the input block allows two modes of operation. in the single data rate (sdr) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. in the ddr mode two registers are used to sample the data on the positive and negative edges of the dqs signal creating two data streams, d0 and d2. these two data streams are synchronized with the system clock before entering the core. further discussion on this topic is in the ddr memory section of this data sheet. figure 2-21 shows the input register waveforms for ddr operation and figure 2-22 shows the design tool primi- tives. the sdr/sync registers have reset and clock enable available. the signal ddrclkpol controls the polarity of the clock used in the synchronization registers. it ensures ade- quate timing when data is transferred from the dqs to the system clock domain. for further discussion of this topic, see the ddr memory section of this data sheet. figure 2-20. input register diagram d q d q d q d-type fixed delay to routing di (from sysio buffer) dqs delayed (from dqs bus) clk0 (from routing) ddrclkpol (from ddr polarity control bus) inck indd delay block ddr registers d-type d-type d q d q d-type /latch /latch d-type ipos0 ipos1 sdr & sync registers d0 d2 d1
2-18 architecture lattice semiconductor latticexp family data sheet figure 2-21. input register ddr waveforms figure 2-22. inddrxb primitive output register block the output register block provides the ability to register signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation that is combined with an additional latch for ddr operation. figure 2-23 shows the diagram of the output register block. in sdr mode, oneg0 feeds one of the ?p-?ps that then feeds the output. the ?p-?p can be con?ured as a d- type or as a latch. in ddr mode, oneg0 is fed into one register on the positive edge of the clock and opos0 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). figure 2-24 shows the design tool ddr primitives. the sdr output register has reset and clock enable available. the additional register for ddr operation does not have reset or clock enable available. abcde f bd di (in ddr mode) d0 d2 dqs a c dqs delayed iddrxb lsr qa d eclk qb ddrclkpol sclk ce
2-19 architecture lattice semiconductor latticexp family data sheet figure 2-23. output register block figure 2-24. oddrxb primitive tristate register block the tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-25 shows the diagram of the tristate register block. in sdr mode, oneg1 feeds one of the ?p-?ps that then feeds the output. the ?p-?p can be con?ured a d- type or latch. in ddr mode, oneg1 is fed into one register on the positive edge of the clock and opos1 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). d q d q d-type oneg0 from routing clk1 *latch is transparent when input is low. programmed control do opos0 outddn /latch latch le* 0 1 0 1 to sysio buffer oddrxb lsr q db clk da
2-20 architecture lattice semiconductor latticexp family data sheet figure 2-25. tristate register block control logic block the control logic block allows the selection and modi?ation of control signals for use in the pio block. a clock is selected from one of the clock signals provided from the general purpose routing and a dqs signal provided from the programmable dqs pin. the clock can optionally be inverted. the clock enable and local reset signals are selected from the routing and optionally inverted. the global tristate signal is passed through this block. ddr memory support implementing high performance ddr memory interfaces requires dedicated ddr register structures in the input (for read operations) and in the output (for write operations). as indicated in the pio logic section, the latticexp devices provide this capability. in addition to these registers, the latticexp devices contain two elements to simplify the design of input structures for read operations: the dqs delay block and polarity control logic. dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment, however in ddr memories the clock (referred to as dqs) is not free running so this approach cannot be used. the dqs delay block provides the required clock alignment for ddr memory interfaces. the dqs signal (selected pios only) feeds from the pad through a dqs delay element to a dedicated dqs rout- ing resource. the dqs signal also feeds the polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. figures 2-26 and 2-27 show how the polarity control logic are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration (6-bit bus) signals from two dlls on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-27. the dll loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. d le* q d q d-type oneg1 clk1 programmed control to opos1 outddn /latch latch 0 1 0 1 from routing to sysio buffer td *latch is transparent when input is low.
2-21 architecture lattice semiconductor latticexp family data sheet figure 2-26. dqs local bus figure 2-27. dll calibration bus and dqs/dqs transition distribution di clki cei pio gsr dqs input register block ( 5 flip flops) to sync. reg. dqs to ddr reg. dqs strobe pa d ddr datain pa d sysio buffer di sysio buffer pio dqsdel polarity control logic dqs calibration bus from dll delay control bus polarity control bus dqs bus dll dll polarity control signal bus dqs signal bus delay control bus
2-22 architecture lattice semiconductor latticexp family data sheet polarity control logic in a typical ddr memory interface design, the phase relation between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticexp family contains dedicated circuits to transfer data between these domains. to prevent setup and hold violations at the domain transfer between dqs (delayed) and the system clock a clock polarity selector is used. this changes the edge on which the data is registered in the synchronizing registers in the input register block. this requires evaluation at the start of the each read cycle for the correct clock polarity. prior to the read operation in ddr memories dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects this transition. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer each i/o is associated with a ?xible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in eight groups referred to as banks. the sysio buffers allow users to implement the wide variety of standards that are found in todays systems including lvcmos, sstl, hstl, lvds and lvpecl. sysio buffer banks latticexp devices have eight sysio buffer banks; each is capable of supporting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ), and two voltage references v ref1 and v ref2 resources allowing each bank to be completely independent from each other. figure 2-28 shows the eight banks and their associated sup- plies. in the latticexp devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos, pci and pci-x) are powered using v ccio . lvttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as a ?ed threshold input independent of v ccio. in addition to the bank v ccio supplies, the latticexp devices have a v cc core logic power sup- ply, and a v ccaux supply that power all differential and referenced buffers. each bank can support up to two separate vref voltages, vref1 and vref2 that set the threshold for the refer- enced input buffers. in the latticexp devices, a dedicated pin in a bank can be con?ured to be a reference voltage supply pin. each i/o is individually con?urable based on the banks supply and reference voltages.
2-23 architecture lattice semiconductor latticexp family data sheet figure 2-28. latticexp banks latticexp devices contain two types of sysio buffer pairs. 1. top and bottom sysio buffer pair (single-ended outputs only) the sysio buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be con?ured as a differential input. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. only the i/os on the top and bottom banks have pci clamps. note that the pci clamp is enabled after v cc, v ccaux and v ccio are at valid operating levels and the device has been con?ured. 2. left and right sysio buffer pair (differential and single-ended outputs) the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. the refer- enced input buffer can also be con?ured as a differential input. in these banks the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. select i/os in the left and right banks have lvds differential output drivers. refer to the logic signal connec- tions tables for more information. v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd note: n and m are the maximum number of i/os per bank. bank 6 v ccio6 v ref2(6) v ref1(5) gnd bank 5 v ccio5 v ref2(5) v ref1(4) gnd bank 4 v ccio4 v ref2(4) v ref1( 0) gnd bank 0 v ccio0 v ref2( 0) v ref1(1) gnd bank 1 v ccio1 v ref2(1) 1 m 1 m 1 m 1 m 1n 1n 1n 1n
2-24 architecture lattice semiconductor latticexp family data sheet typical i/o behavior during power-up the internal power-on-reset (por) signal is deactivated when v cc and v ccaux have reached satisfactory levels. after the por signal is deactivated, the fpga core logic becomes active. it is the users responsibility to ensure that all other v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. the default con?uration of the i/o pins in a blank device is tri-state with a weak pull-up to vccio. the i/o pins will not take on the user con?uration until vcc, vccaux and vccio have reached satisfactory levels at which time the i/os will take on the user-con?ured settings. the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buff- ers. in order to simplify system design while providing consistent and predictable i/o behavior, it is recommended that the i/o buffers be powered-up prior to the fpga core fabric. v ccio supplies should be powered up before or together with the v cc and v ccaux supplies. supported standards the latticexp sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5 and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually con?urable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other sin- gle-ended standards supported include sstl and hstl. differential standards supported include lvds, blvds, lvpecl, differential sstl and differential hstl. tables 2-7 and 2-8 show the i/o standards (together with their supply and reference voltages) supported by the latticexp devices. for further information on utilizing the sysio buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet. table 2-7. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces lvttl lvcmos33 2 lvcmos25 2 lvcmos18 1.8 lvcmos15 1.5 lvcmos12 2 pci 3.3 hstl18 class i, ii 0.9 hstl18 class iii 1.08 hstl15 class i 0.75 hstl15 class iii 0.9 sstl3 class i, ii 1.5 sstl2 class i, ii 1.25 sstl18 class i 0.9 differential interfaces differential sstl18 class i differential sstl2 class i, ii differential sstl3 class i, ii differential hstl15 class i, iii differential hstl18 class i, ii, iii lvds, lvpecl blvds 1. when not speci?d v ccio can be set anywhere in the valid operating range. 2. jtag inputs do not have a ?ed threshold option and always follow v ccj.
2-25 architecture lattice semiconductor latticexp family data sheet table 2-8. supported output standards hot socketing the latticexp devices have been carefully designed to ensure predictable behavior during power-up and power- down. power supplies can be sequenced in any order. during power up and power-down sequences, the i/os remain in tristate until the power supply voltage is high enough to ensure reliable operation. in addition, leakage into i/o pins is controlled to within speci?d limits, which allows easy integration with the rest of the system. these capabilities make the latticexp ideal for many multiple power supply and hot-swap applications. sleep mode the latticexp ? devices (v cc = 1.8/2.5/3.3v) have a sleep mode that allows standby current to be reduced by up to three orders of magnitude during periods of system inactivity. entry and exit to sleep mode is controlled by the sleepn pin. during sleep mode, the fpga logic is non-operational, registers and ebr contents are not maintained and i/os are tri-stated. do not enter sleep mode during device programming or con?uration operation. in sleep mode, power supplies can be maintained in their normal operating range, eliminating the need for external switching of power supplies. table 2-9 compares the characteristics of normal, off and sleep modes. output standard drive v ccio (nom.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 lvcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 lvcmos25 4ma, 8ma, 12ma 16ma, 20ma 2.5 lvcmos18 4ma, 8ma, 12ma 16ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma lvcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma lvcmos18, open drain 4ma, 8ma, 12ma 16ma lvcmos15, open drain 4ma, 8ma lvcmos12, open drain 2ma. 6ma pci33 n/a 3.3 hstl18 class i, ii, iii n/a 1.8 hstl15 class i, iii n/a 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i, ii n/a 2.5 sstl18 class i n/a 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i, ii n/a 2.5 differential sstl18, class i n/a 1.8 differential hstl18, class i, ii, iii n/a 1.8 differential hstl15, class i, iii n/a 1.5 lvds n/a 2.5 blvds 1 n/a 2.5 lvpecl 1 n/a 3.3 1. emulated with external resistors.
2-26 architecture lattice semiconductor latticexp family data sheet table 2-9. characteristics of normal, off and sleep modes sleepn pin characteristics the sleepn pin behaves as an lvcmos input with the voltage standard appropriate to the vcc supply for the device. this pin also has a weak pull-up typically in the order of 10? along with a schmidt trigger and glitch ?ter to prevent false triggering. an external pull-up to v cc is recommended when sleep mode is not used to ensure the device stays in normal operation mode. typically the device enters sleep mode several hundred ns after sleepn is held at a valid low and restarts normal operation as speci?d in the sleep mode timing table. the ac and dc speci?ations portion of this data sheet show a detailed timing diagram. con?uration and testing the following section describes the con?uration and testing features of the latticexp family of devices. ieee 1149.1-compliant boundary scan testability all latticexp devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri?ation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. for more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device con?uration all latticexp devices contain two possible ports that can be used for device con?uration and programming. the test access port (tap), which supports serial con?uration, and the sysconfig port that supports both byte-wide and serial con?uration. the non-volatile memory in the latticexp can be con?ured in three different modes: in sysconfig mode via the sysconfig port. note this can also be done in background mode. in 1532 mode via the 1149.1 port. in background mode via the 1149.1 port. this allows the device to be operated while reprogramming takes place. the sram con?uration memory can be con?ured in three different ways: at power-up via the on-chip non-volatile memory. in 1532 mode via the 1149.1 port sram direct con?uration. in sysconfig mode via the sysconfig port sram direct con?uration. characteristic normal off sleep sleepn pin high low static icc typical <100ma 0 typical <100ua i/o leakage <10? <1ma <10? power supplies vcc/vccio/vccaux normal range off normal range logic operation user de?ed non operational non operational i/o operation user de?ed tri-state tri-state jtag and programming circuitry operational non-operational non-operational ebr contents and registers maintained non-maintained non-maintained
2-27 architecture lattice semiconductor latticexp family data sheet figure 2-29 provides a pictorial representation of the different programming ports and modes available in the lat- ticexp devices. on power-up, the fpga sram is ready to be con?ured with the sysconfig port active. the ieee 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the tap port. leave alone i/o when using 1532 mode for non-volatile memory programming, users may specify i/os as high, low, tristated or held at current value. this provides excellent ?xibility for implementing systems where reprogramming occurs on- the-?. transfr (t rans parent f ield r econ?uration) transfr (tfr) is a unique lattice technology that allows users to update their logic in the ?ld without interrupting system operation using a single ispvm command. see lattice technical note #tn1087, minimizing system inter- ruption during con?uration using transfr technology, for details. security the latticexp devices contain security bits that, when set, prevent the readback of the sram con?uration and non-volatile memory spaces. once set, the only way to clear security bits is to erase the memory space. for more information on device con?uration, please see details of additional technical documentation at the end of this data sheet. figure 2-29. ispxp block diagram internal logic analyzer capability (isptracy) all latticexp devices support an internal logic analyzer diagnostic feature. the diagnostic features provide capabil- ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem- ory. this feature is enabled by lattices isptracy. the isptracy utility is added into the user design at compile time. for more information on isptracy, please see information regarding additional technical documentation at the end of this data sheet. oscillator every latticexp device has an internal cmos oscillator which is used to derive a master serial clock for con?ura- tion. the oscillator and the master serial clock run continuously in the con?uration mode. the default value of the isp 1149.1 tap port sysconfig peripherial port backgnd 1532 sysconfig sram memory space memory space configure in milliseconds program in seconds download in microseconds power-up refresh port mode memory space
2-28 architecture lattice semiconductor latticexp family data sheet master serial clock is 2.5mhz. table 2-10 lists all the available master serial clock frequencies. when a different master serial clock is selected during the design process, the following sequence takes place: 1. user selects a different master serial clock frequency for con?uration. 2. during con?uration the device starts with the default (2.5mhz) master serial clock frequency. 3. the clock con?uration settings are contained in the early con?uration bit stream. 4. the master serial clock frequency changes to the selected frequency once the clock con?uration bits are received. for further information on the use of this oscillator for con?uration, please see details of additional technical docu- mentation at the end of this data sheet. table 2-10. selectable master serial clock (cclk) frequencies during con?uration density shifting the latticexp family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is also possible to shift a lower utilization design tar- geted for a high-density device to a lower density device. however, the exact details of the ?al resource utilization will impact the likely success in each case. cclk (mhz) cclk (mhz) cclk (mhz) 2.5 1 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 10.0 41 1. default
november 2007 data sheet ds1001 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 3-1 ds1001 dc and switching_02.7 recommended operating conditions 3 absolute maximum ratings 1, 2, 3, 4 1. stress above those listed under the ?bsolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or any other conditions outside of those indicated in the operational sections of this speci?ation is not impl ied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. 4. all chip grounds are connected together to a common package gnd plane. xpe (1.2v) xpc (1.8v/2.5v/3.3v) supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccp . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccaux . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v i/o tristate voltage applied 5 . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v dedicated input voltage applied 5 . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 4.25v storage temperature (ambient) . . . . . . . . . . . . . . -65 to 150? . . . . . . . . . . . . . . . -65 to 150? junction temp. (tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125? . . . . . . . . . . . . . . . . . . . +125? 5. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc core supply voltage for 1.2v devices 1.14 1.26 v core supply voltage for 1.8v/2.5v/3.3v devices 1.71 3.465 v v ccp supply voltage for pll for 1.2v devices 1.14 1.26 v supply voltage for pll for 1.8v/2.5v/3.3v devices 1.71 3.465 v v ccaux 4 auxiliary supply voltage 3.135 3.465 v v ccio 1, 2 i/o driver supply voltage 1.14 3.465 v v ccj 1 supply voltage for ieee 1149.1 test access port 1.14 3.465 v t jcom junction temperature, commercial operation 0 85 c t jind junction temperature, industrial operation -40 100 c t jflashcom junction temperature, flash programming, commercial 0 85 c t jflashind junction temperature, flash programming, industrial 0 85 c 1. if v ccio or v ccj is set to 3.3v, they must be connected to the same power supply as v ccaux. for the xpe devices (1.2v v cc ), if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc . 2. see recommended voltages by i/o standard in subsequent table. 3. the system designer must ensure that the fpga design stays within the speci?d junction temperature and package thermal capab ilities of the device based on the expected operating frequency, activity factor and environment conditions of the system. 4. v ccaux ramp rate must not exceed 30mv/? during power up when transitioning between 0v and 3.3v. latticexp family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor latticexp family data sheet hot socketing speci?ations 1, 2, 3, 4, 5, 6 1. insensitive to sequence of v cc, v ccaux and v ccio . however, assumes monotonic rise/fall rates for v cc, v ccaux and v ccio. 2. 0 v cc v cc (max) or 0 v ccaux v ccaux (max). 3. 0 v ccio v ccio (max) for top and bottom i/o banks. 4. 0.2 v ccio v ccio (max) for left and right i/o banks. 5. i dk is additive to i pu, i pw or i bh . 6. lvcmos and lvttl only. symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 v in v ih (max.) +/-1000 ?
3-3 dc and switching characteristics lattice semiconductor latticexp family data sheet dc electrical characteristics over recommended operating conditions supply current (sleep mode) 1, 2, 3 symbol parameter condition min. typ. max. units i il, i ih 1, 2, 4 input or i/o leakage 0 v in (v ccio - 0.2v) 10 ? (v ccio - 0.2v) < v in 3.6v 40 ? i pu i/o active pull-up current 0 v in 0.7 v ccio -30 -150 ? i pd i/o active pull-down current v il (max) v in v ih (max) 30 150 ? i bhls bus hold low sustaining current v in = v il (max) 30 ? i bhhs bus hold high sustaining current v in = 0.7v ccio -30 ? i bhlo bus hold low overdrive current 0 v in v ih (max) 150 ? i bhho bus hold high overdrive current 0 v in v ih (max) -150 ? v bht bus hold trip points 0 v in v ih (max) v il (max) v ih (min) v c1 i/o capacitance 3 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?pf c2 dedicated input capacitance 3 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?pf 1. input or i/o leakage current is measured with the pin con?ured as an input or as an i/o with the output driver tri-stated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. not applicable to sleepn/toe pin. 3. t a 25?, f = 1.0mhz 4. when v ih is higher than v ccio , a transient current typically of 30ns in duration or less with a peak current of 6ma can be expected on the high-to-low transition. symbol parameter device typ. 4 max units i cc core power supply lfxp3c 12 65 ? lfxp6c 14 75 ? lfxp10c 16 85 ? LFXP15c 18 95 ? lfxp20c 20 105 ? i ccp pll power supply (per pll) all lfxp ? devices 1 5 ? i ccaux auxiliary power supply lfxp3c 2 90 a lfxp6c 2 100 ? lfxp10c 2 110 ? LFXP15c 3 120 ? lfxp20c 4 130 ? i ccio bank power supply 5 lfxp3c 2 20 a lfxp6c 2 22 a lfxp10c 2 24 a LFXP15c 3 27 a lfxp20c 4 30 a i ccj vccj power supply all lfxp ? devices 1 5 ? 1. assumes all inputs are con?ured as lvcmos and held at the vccio or gnd. 2. frequency 0mhz. 3. user pattern: blank. 4. t a =25?, power supplies at nominal voltage. 5. per bank.
3-4 dc and switching characteristics lattice semiconductor latticexp family data sheet supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5 units i cc core power supply lfxp3e 15 ma lfxp6e 20 ma lfxp10e 35 ma LFXP15e 45 ma lfxp20e 55 ma lfxp3c 35 ma lfxp6c 40 ma lfxp10c 70 ma LFXP15c 80 ma lfxp20c 90 ma i ccp pll power supply (per pll) all 8 ma i ccaux auxiliary power supply v ccaux = 3.3v lfxp3e/c 22 ma lfxp6e/c 22 ma lfxp10e/c 30 ma LFXP15e/c 30 ma lfxp20e/c 30 ma i ccio bank power supply 6 all 2 ma i ccj v ccj power supply all 1 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the vccio or gnd. 3. frequency 0mhz. 4. user pattern: blank. 5. t a =25?, power supplies at nominal voltage. 6. per bank.
3-5 dc and switching characteristics lattice semiconductor latticexp family data sheet initialization supply current 1, 2, 3, 4, 5, 6 over recommended operating conditions symbol parameter device typ. 7 units i cc core power supply lfxp3e 40 ma lfxp6e 50 ma lfxp10e 110 ma LFXP15e 140 ma lfxp20e 250 ma lfxp3c 60 ma lfxp6c 70 ma lfxp10c 150 ma LFXP15c 180 ma lfxp20c 290 ma i ccaux auxiliary power supply v ccaux = 3.3v lfxp3e /c 50 ma lfxp6e /c 60 ma lfxp10e /c 90 ma LFXP15e /c 110 ma lfxp20e /c 130 ma i ccj v ccj power supply all 2 ma 1. until done signal is active. 2. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 3. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. typical user pattern. 6. assume normal bypass capacitor/decoupling capacitor across the supply. 7. t a =25?, power supplies at nominal voltage.
3-6 dc and switching characteristics lattice semiconductor latticexp family data sheet programming and erase flash supply current 1, 2, 3, 4, 5 symbol parameter device typ .6 units i cc core power supply lfxp3e 30 ma lfxp6e 40 ma lfxp10e 50 ma LFXP15e 60 ma lfxp20e 70 ma lfxp3c 50 ma lfxp6c 60 ma lfxp10c 90 ma LFXP15c 100 ma lfxp20c 110 ma i ccaux auxiliary power supply v ccaux = 3.3v lfxp3e /c 50 ma lfxp6e /c 60 ma lfxp10e /c 90 ma LFXP15e /c 110 ma lfxp20e /c 130 ma i ccj v ccj power supply 7 all 2 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 3. blank user pattern; typical flash pattern. 4. bypass or decoupling capacitor across the supply. 5. jtag programming is at 1mhz. 6. t a =25?, power supplies at nominal voltage. 7. when programming via jtag.
3-7 dc and switching characteristics lattice semiconductor latticexp family data sheet sysio recommended operating conditions v ccio v ref (v) standard min. typ. max. min. typ. max. lvcmos 3.3 3.135 3.3 3.465 lvcmos 2.5 2.375 2.5 2.625 lvcmos 1.8 1.71 1.8 1.89 lvcmos 1.5 1.425 1.5 1.575 lvcmos 1.2 1.14 1.2 1.26 lvttl 3.135 3.3 3.465 pci33 3.135 3.3 3.465 sstl18 class i 1.71 1.8 1.89 0.833 0.9 0.969 sstl2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl15 class iii 1.425 1.5 1.575 0.9 hstl 18 class i, ii 1.71 1.8 1.89 0.9 hstl 18 class iii 1.71 1.8 1.89 1.08 lvds 2.375 2.5 2.625 lvpecl 1 3.135 3.3 3.465 blvds 1 2.375 2.5 2.625 1. inputs on chip. outputs are implemented with the addition of external resistors.
3-8 dc and switching characteristics lattice semiconductor latticexp family data sheet sysio single-ended dc electrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol (ma) i oh (ma) min. (v) max. (v) min. (v) max. (v) lvcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvttl -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.8 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.5 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 (? version) -0.3 0.42 0.78 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 (? version) -0.3 0.35v cc 0.65v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3v ccio 0.5v ccio 3.6 0.1v ccio 0.9v ccio 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 sstl18 class i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 hstl15 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8 -8 hstl15 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 hstl18 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 9.6 -9.6 hstl18 class ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 hstl18 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma. where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-9 dc and switching characteristics lattice semiconductor latticexp family data sheet sysio differential electrical characteristics lvds over recommended operating conditions parameter symbol parameter description test conditions min. typ. max. units v inp, v inm input voltage 0 2.4 v v thd differential input threshold +/-100 mv v cm input common mode voltage 100mv v thd v thd /2 1.2 1.8 v 200mv v thd v thd /2 1.2 1.9 v 350mv v thd v thd /2 1.2 2.0 v i in input current power on or power off +/-10 ? v oh output high voltage for v op or v om r t = 100 ohms 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohms 0.9v 1.03 v v od output voltage differential (v op - v om ), r t = 100 ohms 250 350 450 mv v od change in v od between high and low 50 mv v os output voltage offset (v op - v om )/2, r t = 100 ohms 1.125 1.25 1.375 v v os change in v os between h and l 50 mv i osd output short circuit current v od = 0v driver outputs shorted 6ma
3-10 dc and switching characteristics lattice semiconductor latticexp family data sheet differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output classes (class i and class ii) are supported in this mode. lvds25e the top and bottom side of latticexp devices support lvds outputs via emulated complementary lvcmos out- puts in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-1 is one possi- ble solution for point-to-point signals. figure 3-1. lvds25e output termination example table 3-1. lvds25e dc conditions over recommended operating conditions blvds the latticexp devices support blvds standard. this standard is emulated using complementary lvcmos out- puts in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when multi- drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. parameter description typical units v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differential voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100 i dc dc output current 3.66 ma + - bo u rns cat16-l v 4f12 rs=165 ohms (?%) rs=165 ohms (?%) rd = 140 ohms (?%) rd = 100 ohms (?%) off-chip transmission line, zo = 100 ohm differential v ccio = 2.5 v (?%) v ccio = 2.5 v (?%) o n -chip off-chip o n -chip
3-11 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-2. blvds multi-point output example table 3-2. blvds dc conditions 1 over recommended operating conditions typical symbol description zo = 45 zo = 90 units z out output impedance 100 100 ohms r tleft left end termination 45 90 ohms r tright right end termination 45 90 ohms v oh output high voltage 1.375 1.48 v v ol output low voltage 1.125 1.02 v v od output differential voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.2 10.2 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v 80 80 80 80 80 80 45-90 ohms 45-90 ohms 80 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + -
3-12 dc and switching characteristics lattice semiconductor latticexp family data sheet lvpecl the latticexp devices support differential lvpecl standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the lvpecl input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-3 is one possible solution for point- to-point signals. figure 3-3. differential lvpecl table 3-3. lvpecl dc conditions 1 over recommended operating conditions for further information on lvpecl, blvds and other differential interfaces please see details of additional techni- cal documentation at the end of the data sheet. rsds the latticexp devices support differential rsds standard. this standard is emulated using complementary lvc- mos outputs in conjunction with a parallel resistor across the driver outputs. the rsds input standard is sup- ported by the lvds differential input buffer. the scheme shown in figure 3-4 is one possible solution for rsds standard implementation. use lvds25e mode with suggested resistors for rsds operation. resistor values in figure 3-4 are industry standard values for 1 % resistors. symbol description typical units z out output impedance 100 ohms r p driver parallel resistor 187 ohms r s driver series resistor 100 ohms r t receiver termination 100 ohms v oh output high voltage 2.03 v v ol output low voltage 1.27 v v od output differential voltage 0.76 v v cm output common mode voltage 1.65 v z back back impedance 85.7 ohms i dc dc output current 12.7 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential r s = 100 ohms = 100 ohms = 187 ohms = 100 ohms r s r p r t off-chip 3.3v 3.3v + -
3-13 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-4. rsds (reduced swing differential standard) table 3-4. rsds dc conditions parameter description typical units z out output impedance 20 ohms r s driver series resistor 300 ohms r p driver parallel resistor 121 ohms r t receiver termination 100 ohms v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ohms i dc dc output current 3.66 ma r s r s r p r t on-chip emulated rsds buffer vccio = 2.5v vccio = 2.5v zo = 100 + - off-chip
3-14 dc and switching characteristics lattice semiconductor latticexp family data sheet typical building block function performance 1 pin-to-pin performance (lvcmos25 12 ma drive) register to register performance function -5 timing units basic functions 16-bit decoder 6.1 ns 32-bit decoder 7.3 ns 64-bit decoder 8.2 ns 4:1 mux 4.9 ns 8:1 mux 5.3 ns 16:1 mux 5.7 ns 32:1 mux 6.3 ns function -5 timing units basic functions 16-bit decoder 351 mhz 32-bit decoder 248 mhz 64-bit decoder 237 mhz 4:1 mux 590 mhz 8:1 mux 523 mhz 16:1 mux 434 mhz 32:1 mux 355 mhz 8-bit adder 343 mhz 16-bit adder 292 mhz 64-bit adder 130 mhz 16-bit counter 388 mhz 32-bit counter 295 mhz 64-bit counter 200 mhz 64-bit accumulator 164 mhz embedded memory functions single port ram 256x36 bits 254 mhz true-dual port ram 512x18 bits 254 mhz distributed memory functions 16x2 sp ram 434 mhz 64x2 sp ram 332 mhz 128x4 sp ram 235 mhz 32x2 pdp ram 322 mhz 64x4 pdp ram 291 mhz 1. these timing numbers were generated using the isplever design tool. exact performance may vary with design and tool version. the tool uses internal parameters that have been characterized but are not tested on every device. timing v.f0.11
3-15 dc and switching characteristics lattice semiconductor latticexp family data sheet derating logic timing logic timing provided in the following sections of this data sheet and in the isplever design tools are worst case numbers in the operating range. actual delays at nominal temperature and voltage for best-case process can be much better than the values given in the tables. the isplever design tool from lattice can provide logic timing numbers at a particular temperature and voltage.
3-16 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp external switching characteristics over recommended operating conditions parameter description device -5 -4 -3 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register lfxp3 5.12 6.12 7.43 ns lfxp6 5.30 6.34 7.69 ns lfxp10 5.52 6.60 8.00 ns LFXP15 5.72 6.84 8.29 ns lfxp20 5.97 7.14 8.65 ns t su clock to data setup - pio input register lfxp3 -0.40 -0.28 -0.16 ns lfxp6 -0.33 -0.32 -0.30 ns lfxp10 -0.61 -0.71 -0.81 ns LFXP15 -0.71 -0.77 -0.87 ns lfxp20 -0.95 -1.14 -1.35 ns t h clock to data hold - pio input register lfxp3 2.10 2.50 2.98 ns lfxp6 2.28 2.72 3.24 ns lfxp10 3.02 3.51 3.71 ns LFXP15 2.70 3.22 3.85 ns lfxp20 2.95 3.52 4.21 ns t su_del clock to data setup - pio input register with input data delay lfxp3 2.38 2.49 2.66 ns lfxp6 2.92 3.18 3.42 ns lfxp10 2.72 2.75 2.84 ns LFXP15 2.99 3.13 3.18 ns lfxp20 4.47 4.56 4.80 ns t h_del clock to data hold - pio input register with input data delay lfxp3 -0.70 -0.80 -0.92 ns lfxp6 -0.47 -0.38 -0.31 ns lfxp10 -0.60 -0.47 -0.32 ns LFXP15 -1.05 -0.98 -1.01 ns lfxp20 -0.80 -0.58 -0.31 ns f max_io clock frequency of i/o and pfu register all 400 360 320 mhz ddr i/o pin parameters 2 t dvadq data valid after dqs (ddr read) all 0.19 0.19 0.19 ui t dvedq data hold after dqs (ddr read) all 0.67 0.67 0.67 ui t dqvbs data valid before dqs all 0.20 0.20 0.20 ui t dqvas data valid after dqs all 0.20 0.20 0.20 ui f max_ddr ddr clock frequency all 95 166 95 133 95 100 mhz primary and secondary clocks f max_pri frequency for primary clock tree all 450 412 375 mhz t w_pri clock pulse width for primary clock all 1.19 1.19 1.19 ns t skew_pri primary clock skew within an i/o bank lfxp3/6/10/15 250 300 350 ps lfxp20 300 350 400 ps 1. general timing numbers based on lvcmos 2.5, 12ma. 2. ddr timing numbers based on sstl i/o. timing v.f0.11
3-17 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-5. ddr timings t dqvas t dqvbs dq and dqs write timings t dqs dq dqs dq dvedq t dvadq dq and dqs read timings
3-18 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp internal timing parameters 1 over recommended operating conditions parameter description -5 -4 -3 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) 0.28 0.34 0.40 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) 0.44 0.53 0.63 ns t lsr_pfu set/reset to output of pfu 0.90 1.08 1.29 ns t sum_pfu clock to mux (m0,m1) input setup time 0.13 0.15 0.19 ns t hm_pfu clock to mux (m0,m1) input hold time -0.04 -0.03 -0.03 ns t sud_pfu clock to d input setup time 0.13 0.16 0.19 ns t hd_pfu clock to d input hold time -0.03 -0.02 -0.02 ns t ck2q_pfu clock to q delay, d-type register con?uration 0.40 0.48 0.58 ns t le2q_pfu clock to q delay latch con?uration 0.53 0.64 0.76 ns t ld2q_pfu d to q throughput delay when latch is enabled 0.55 0.66 0.79 ns pfu dual port memory mode timing t coram_pfu clock to output 0.40 0.48 0.58 ns t sudata_pfu data setup time -0.18 -0.14 -0.11 ns t hdata_pfu data hold time 0.28 0.34 0.40 ns t suaddr_pfu address setup time -0.46 -0.37 -0.30 ns t haddr_pfu address hold time 0.71 0.85 1.02 ns t suwren_pfu write/read enable setup time -0.22 -0.17 -0.14 ns t hwren_pfu write/read enable hold time 0.33 0.40 0.48 ns pic timing pio input/output buffer timing t in_pio input buffer delay 0.62 0.72 0.85 ns t out_pio output buffer delay 2.12 2.54 3.05 ns iologic input/output timing t sui_pio input register setup time (data before clock) 1.35 1.83 2.37 ns t hi_pio input register hold time (data after clock) 0.05 0.05 0.05 ns t coo_pio output register clock to output delay 0.36 0.44 0.52 ns t suce_pio input register clock enable setup time -0.09 -0.07 -0.06 ns t hce_pio input register clock enable hold time 0.13 0.16 0.19 ns t sulsr_pio set/reset setup time 0.19 0.23 0.28 ns t hlsr_pio set/reset hold time -0.14 -0.11 -0.09 ns ebr timing t co_ebr clock to output from address or data 4.01 4.81 5.78 ns t coo_ebr clock to output from ebr output register 0.81 0.97 1.17 ns t sudata_ebr setup data to ebr memory -0.26 -0.21 -0.17 ns t hdata_ebr hold data to ebr memory 0.41 0.49 0.59 ns t suaddr_ebr setup address to ebr memory -0.26 -0.21 -0.17 ns t haddr_ebr hold address to ebr memory 0.41 0.49 0.59 ns t suwren_ebr setup write/read enable to ebr memory -0.17 -0.13 -0.11 ns t hwren_ebr hold write/read enable to ebr memory 0.26 0.31 0.37 ns t suce_ebr clock enable setup time to ebr output register 0.19 0.23 0.28 ns t hce_ebr clock enable hold time to ebr output register -0.13 -0.10 -0.08 ns
3-19 dc and switching characteristics lattice semiconductor latticexp family data sheet t rsto_ebr reset to output delay time from ebr output register 1.61 1.94 2.32 ns pll parameters t rstrec reset recovery to rising clock 1.00 1.00 1.00 ns t rstsu reset signal setup time 1.00 1.00 1.00 ns 1. internal parameters are characterized but not tested on every device. timing v.f0.11 latticexp internal timing parameters 1 (continued) over recommended operating conditions parameter description -5 -4 -3 units min. max. min. max. min. max.
3-20 dc and switching characteristics lattice semiconductor latticexp family data sheet timing diagrams pfu timing diagrams figure 3-6. slice single/dual port write cycle timing figure 3-7. slice single /dual port read cycle timing ck d wre d di[1:0] do[1:0] ad ad[3:0] old data wre d do[1:0] ad ad[3:0] old data
3-21 dc and switching characteristics lattice semiconductor latticexp family data sheet ebr memory timing diagrams figure 3-8. read mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. figure 3-9. read mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t access t access t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 d0 d0 doa output is only updated during a read cycle a1 d1 d0 d1 mem(n) data from previous read mem(n) data from previous read dia ada wea csa clka doa doa (registered) t su t h t access t access
3-22 dc and switching characteristics lattice semiconductor latticexp family data sheet figure 3-10. read before write (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. figure 3-11. write through (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. a0 a1 a0 a1 d0 d1 d2 doa a0 d2 d3 d1 old a0 data old a1 data d0 d1 dia ada wea csa clka t su t h t access t access t access t access t access a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access
3-23 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp family timing adders 1 over recommended operating conditions buffer type description -5 -4 -3 units input adjusters lvds25e lvds 2.5 emulated 0.5 0.5 0.5 ns lvds25 lvds 0.4 0.4 0.4 ns blvds25 blvds 0.5 0.5 0.5 ns lvpecl33 lvpecl 0.6 0.6 0.6 ns hstl18_i hstl_18 class i 0.4 0.4 0.4 ns hstl18_ii hstl_18 class ii 0.4 0.4 0.4 ns hstl18_iii hstl_18 class iii 0.4 0.4 0.4 ns hstl18d_i differential hstl 18 class i 0.4 0.4 0.4 ns hstl18d_ii differential hstl 18 class ii 0.4 0.4 0.4 ns hstl18d_iii differential hstl 18 class iii 0.4 0.4 0.4 ns hstl15_i hstl_15 class i 0.5 0.5 0.5 ns hstl15_iii hstl_15 class iii 0.5 0.5 0.5 ns hstl15d_i differential hstl 15 class i 0.5 0.5 0.5 ns hstl15d_iii differential hstl 15 class iii 0.5 0.5 0.5 ns sstl33_i sstl_3 class i 0.6 0.6 0.6 ns sstl33_ii sstl_3 class ii 0.6 0.6 0.6 ns sstl33d_i differential sstl_3 class i 0.6 0.6 0.6 ns sstl33d_ii differential sstl_3 class ii 0.6 0.6 0.6 ns sstl25_i sstl_2 class i 0.5 0.5 0.5 ns sstl25_ii sstl_2 class ii 0.5 0.5 0.5 ns sstl25d_i differential sstl_2 class i 0.5 0.5 0.5 ns sstl25d_ii differential sstl_2 class ii 0.5 0.5 0.5 ns sstl18_i sstl_18 class i 0.5 0.5 0.5 ns sstl18d_i differential sstl_18 class i 0.5 0.5 0.5 ns lvttl33 lvttl 0.2 0.2 0.2 ns lvcmos33 lvcmos 3.3 0.2 0.2 0.2 ns lvcmos25 lvcmos 2.5 0.0 0.0 0.0 ns lvcmos18 lvcmos 1.8 0.1 0.1 0.1 ns lvcmos15 lvcmos 1.5 0.1 0.1 0.1 ns lvcmos12 lvcmos 1.2 0.1 0.1 0.1 ns pci33 pci 0.2 0.2 0.2 ns output adjusters lvds25e lvds 2.5 emulated 0.3 0.3 0.3 ns lvds25 lvds 2.5 0.3 0.3 0.3 ns blvds25 blvds 2.5 0.3 0.3 0.3 ns lvpecl33 lvpecl 3.3 0.1 0.1 0.1 ns hstl18_i hstl_18 class i 0.1 0.1 0.1 ns hstl18_ii hstl_18 class ii 0.1 0.1 0.1 ns hstl18_iii hstl_18 class iii 0.2 0.2 0.2 ns hstl18d_i differential hstl 18 class i 0.1 0.1 0.1 ns hstl18d_ii differential hstl 18 class ii -0.1 -0.1 -0.1 ns hstl18d_iii differential hstl 18 class iii 0.2 0.2 0.2 ns
3-24 dc and switching characteristics lattice semiconductor latticexp family data sheet hstl15_i hstl_15 class i 0.2 0.2 0.2 ns hstl15_iii hstl_15 class iii 0.2 0.2 0.2 ns hstl15d_i differential hstl 15 class i 0.2 0.2 0.2 ns hstl15d_iii differential hstl 15 class iii 0.2 0.2 0.2 ns sstl33_i sstl_3 class i 0.1 0.1 0.1 ns sstl33_ii sstl_3 class ii 0.3 0.3 0.3 ns sstl33d_i differential sstl_3 class i 0.1 0.1 0.1 ns sstl33d_ii differential sstl_3 class ii 0.3 0.3 0.3 ns sstl25_i sstl_2 class i -0.1 -0.1 -0.1 ns sstl25_ii sstl_2 class ii 0.3 0.3 0.3 ns sstl25d_i differential sstl_2 class i -0.1 -0.1 -0.1 ns sstl25d_ii differential sstl_2 class ii 0.3 0.3 0.3 ns sstl18_i sstl_1.8 class i 0.1 0.1 0.1 ns sstl18d_i differential sstl_1.8 class i 0.1 0.1 0.1 ns lvttl33_4ma lvttl 4ma drive 0.8 0.8 0.8 ns lvttl33_8ma lvttl 8ma drive 0.5 0.5 0.5 ns lvttl33_12ma lvttl 12ma drive 0.3 0.3 0.3 ns lvttl33_16ma lvttl 16ma drive 0.4 0.4 0.4 ns lvttl33_20ma lvttl 20ma drive 0.3 0.3 0.3 ns lvcmos33_2ma lvcmos 3.3 2ma drive 0.8 0.8 0.8 ns lvcmos33_4ma lvcmos 3.3 4ma drive 0.8 0.8 0.8 ns lvcmos33_8ma lvcmos 3.3 8ma drive 0.5 0.5 0.5 ns lvcmos33_12ma lvcmos 3.3 12ma drive 0.3 0.3 0.3 ns lvcmos33_16ma lvcmos 3.3 16ma drive 0.4 0.4 0.4 ns lvcmos33_20ma lvcmos 3.3 20ma drive 0.3 0.3 0.3 ns lvcmos25_2ma lvcmos 2.5 2ma drive 0.7 0.7 0.7 ns lvcmos25_4ma lvcmos 2.5 4ma drive 0.7 0.7 0.7 ns lvcmos25_8ma lvcmos 2.5 8ma drive 0.4 0.4 0.4 ns lvcmos25_12ma lvcmos 2.5 12ma drive 0.0 0.0 0.0 ns lvcmos25_16ma lvcmos 2.5 16ma drive 0.2 0.2 0.2 ns lvcmos25_20ma lvcmos 2.5 20ma drive 0.4 0.4 0.4 ns lvcmos18_2ma lvcmos 1.8 2ma drive 0.6 0.6 0.6 ns lvcmos18_4ma lvcmos 1.8 4ma drive 0.6 0.6 0.6 ns lvcmos18_8ma lvcmos 1.8 8ma drive 0.4 0.4 0.4 ns lvcmos18_12ma lvcmos 1.8 12ma drive 0.2 0.2 0.2 ns lvcmos18_16ma lvcmos 1.8 16ma drive 0.2 0.2 0.2 ns lvcmos15_2ma lvcmos 1.5 2ma drive 0.6 0.6 0.6 ns lvcmos15_4ma lvcmos 1.5 4ma drive 0.6 0.6 0.6 ns lvcmos15_8ma lvcmos 1.5 8ma drive 0.2 0.2 0.2 ns lvcmos12_2ma lvcmos 1.2 2ma drive 0.4 0.4 0.4 ns lvcmos12_6ma lvcmos 1.2 6ma drive 0.4 0.4 0.4 ns pci33 pci33 0.3 0.3 0.3 ns 1. general timing numbers based on lvcmos 2.5, 12ma. timing v.f0.11 latticexp family timing adders 1 (continued) over recommended operating conditions buffer type description -5 -4 -3 units
3-25 dc and switching characteristics lattice semiconductor latticexp family data sheet sysclock pll timing over recommended operating conditions latticexp ? sleep mode timing parameter descriptions conditions min. typ. max. units f in input clock frequency (clki, clkfb) 25 375 mhz f out output clock frequency (clkop, clkos) 25 375 mhz f out2 k-divider output frequency (clkok) 0.195 187.5 mhz f vco pll vco frequency 375 750 mhz f pfd phase detector input frequency 25 mhz ac characteristics t dt output clock duty cycle default duty cycle elected 3 45 50 55 % t ph 4 output phase accuracy 0.05 ui t opjit 1 output clock period jitter f out 100mhz +/- 125 ps f out < 100mhz 0.02 uipp t sk input clock to output clock skew divider ratio = integer +/- 200 ps t w output clock pulse width at 90 % or 10 % 3 1ns t lock 2 pll lock-in time 150 us t pa programmable delay unit 100 250 400 ps t ipjit input clock period jitter +/- 200 ps t fbkdly external feedback delay 10 ns t hi input clock high time 90 % to 90 % 0.5 ns t lo input clock low time 10 % to 10 % 0.5 ns t rst rst pulse width 10 ns 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference clock. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. as compared to clkop output. timing v.f0.11 parameter descriptions min. typ. max. units t pwrdn sleepn low to i/o tristate 20 32 ns t pwrup sleepn high to power up lfxp3 1.4 2.1 ms lfxp6 1.7 2.4 ms lfxp10 1.1 1.8 ms LFXP15 1.4 2.1 ms lfxp20 1.7 2.4 ms t wsleepn sleepn pulse width to initiate sleep mode 400 ns t wawake sleepn pulse rejection 120 ns sleepn t pwrup sleep mode t pwrdn i/o
3-26 dc and switching characteristics lattice semiconductor latticexp family data sheet latticexp sysconfig port timing speci?ations over recommended operating conditions parameter description min. max. units sysconfig byte data flow t sucbdi byte d[0:7] setup time to cclk 7 ns t hcbdi byte d[0:7] hold time to cclk 3 ns t codo clock to dout in flowthrough mode 12 ns t sucs cs[0:1] setup time to cclk 7 ns t hcs cs[0:1] hold time to cclk 2 ns t suwd write signal setup time to cclk 7 ns t hwd write signal hold time to cclk 2 ns t dcb cclk to busy delay time 12 ns t cord clock to out for read data 12 ns sysconfig byte slave clocking t bsch byte slave clock minimum high pulse 6 ns t bscl byte slave clock minimum low pulse 8 ns t bscyc byte slave clock cycle time 15 ns sysconfig serial (bit) data flow t suscdi di (data in) setup time to cclk 7 ns t hscdi di (data in) hold time to cclk 2 ns t codo clock to dout in flowthrough mode 12 ns sysconfig serial slave clocking t ssch serial slave clock minimum high pulse 6 ns t sscl serial slave clock minimum low pulse 6 ns sysconfig por, initialization and wake up t icfg minimum vcc to init high 50 ms t vmc time from t icfg to valid master clock 2 us t prgmrj program pin pulse rejection 7 ns t prgm 2 programn low time to start con?uration 25 ns t dinit init low time 1 ms t dppinit delay time from programn low to init low 37 ns t dinitd delay time from programn low to done low 37 ns t iodiss user i/o disable from programn low 25 ns t ioenss user i/o enabled time from cclk edge during wake-up sequence 25 ns t mwc additional wake master clock signals after done pin high 120 cycles con?uration master clock (cclk) frequency 1 selected value - 30 % selected value + 30 % mhz duty cycle 40 60 % 1. see table 2-10 for available cclk frequencies. 2. the threshold level for programn, as well as for cfg[1] and cfg[0], is determined by v cc , such that the threshold = v cc /2. timing v.f0.11
3-27 dc and switching characteristics lattice semiconductor latticexp family data sheet flash download time jtag port timing speci?ations over recommended operating conditions figure 3-12. jtag port timing waveforms symbol parameter min. typ. max. units t refresh programn low-to- high. transition to done high. lfxp3 1.1 1.7 ms lfxp6 1.4 2.0 ms lfxp10 0.9 1.5 ms LFXP15 1.1 1.7 ms lfxp20 1.3 1.9 ms symbol parameter min. max. units f max 25 mhz t btcp tck [bscan] clock pulse width 40 ns t btcph tck [bscan] clock pulse width high 20 ns t btcpl tck [bscan] clock pulse width low 20 ns t bts tck [bscan] setup time 10 ns t bth tck [bscan] hold time 8 ns t btrf tck [bscan] rise/fall time 50 ns t btco tap controller falling edge of clock to valid output 10 ns t btcodis tap controller falling edge of clock to valid disable 10 ns t btcoen tap controller falling edge of clock to valid enable 10 ns t btcrs bscan test capture register setup time 8 ns t btcrh bscan test capture register hold time 25 ns t butco bscan test update register, falling edge of clock to valid output 25 ns t btuodis bscan test update register, falling edge of clock to valid disable 25 ns t btupoen bscan test update register, falling edge of clock to valid enable 25 ns timing v.f0.11 tms tdi tck tdo data to b e capt u red from i/o data to b e dri v en o u t to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data capt u red t btcph t btcpl t btcoe n t btcrs t btupoe n t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp
3-28 dc and switching characteristics lattice semiconductor latticexp family data sheet switching test conditions figure 3-13 shows the output test load that is used for ac testing. the speci? values for resistance, capacitance, voltage, and other test conditions are shown in figure 3-5. figure 3-13. output test load, lvttl and lvcmos standards table 3-5. test fixture required components, non-terminated interfaces test condition r 1 c l timing ref. v t lvttl and other lvcmos settings (l -> h, h -> l) 0pf lvcmos 3.3 = 1.5v lvcmos 2.5 = v ccio /2 lvcmos 1.8 = v ccio /2 lvcmos 1.5 = v ccio /2 lvcmos 1.2 = v ccio /2 lvcmos 2.5 i/o (z -> h) 188 0pf v ccio /2 v ol lvcmos 2.5 i/o (z -> l) v ccio /2 v oh lvcmos 2.5 i/o (h -> z) v oh - 0.15 v ol lvcmos 2.5 i/o (l -> z) v ol + 0.15 v oh note: output test conditions for all other interfaces are determined by the respective standards. dut v t r1 cl test poi nt
november 2007 data sheet ds1001 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 4-1 ds1001 pinouts_02.5 signal descriptions signal name i/o descriptions general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or (bottom), only need to specify row number. when edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user programmable pins are shared with special function pins. these pin when not used as special purpose pins can be programmed as i/os for user logic. during con?uration, the user-programmable i/os are tri-stated with an inter- nal pull-up resistor enabled. if any pin is not used (or not bonded to a pack- age pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. gsrn i global reset signal. (active low). any i/o pin can be con?ured to be gsrn. nc no connect. gnd gnd - ground. dedicated pins. v cc vcc - the power supply pins for core logic. dedicated pins. v ccaux v ccaux - the auxiliary power supply pin. it powers all the differential and ref- erenced input buffers. dedicated pins. v ccp0 voltage supply pins for ulm0pll (and llm1pll 1 ). v ccp1 voltage supply pins for urm0pll (and lrm1pll 1 ). gndp0 ground pins for ulm0pll (and llm1pll 1 ). gndp1 ground pins for urm0pll (and lrm1pll 1 ). v cciox ? ccio - the power supply pins for i/o bank x. dedicated pins. v ref1(x), v ref2(x) reference supply pins for i/o bank x. pre-determined pins in each bank are assigned as v ref inputs. when not used, they may be used as i/o pins. pll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_pll[t, c]_in_a reference clock (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a, b, c...at each side. [loc][num]_pll[t, c]_fb_a optional feedback (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a, b, c...at each side. pclk[t, c]_[n:0]_[3:0] primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1, 2, 3 within bank. [loc]dqs[num] dqs input pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. any pad can be con?ured to be dqs output. latticexp family data sheet pinout information
4-2 pinout information lattice semiconductor latticexp family data sheet test and programming (dedicated pins. pull-up is enabled on input pins during con?uration.) tms i test mode select input, used to control the 1149.1 state machine. tck i test clock input pin, used to clock the 1149.1 state machine. tdi i test data in pin, used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for con?uration by sending appropriate command. (note: once a con?uration port is selected it is locked. another con?uration port cannot be selected until the power-up sequence). tdo o output pin -test data out pin used to shift data out of device using 1149.1. v ccj ? ccj - the power supply pin for jtag test access port. con?uration pads (used during sysconfig) cfg[1:0] i mode pins used to specify con?uration modes values latched on rising edge of initn. during con?uration, a pull-up is enabled. initn i/o open drain pin - indicates the fpga is ready to be con?ured. during con- ?uration, a pull-up is enabled. if cfg1 and cfg0 are high (sdm) then this pin is pulled low. programn i initiates con?uration sequence when asserted low. this pin always has an active pull-up. done i/o open drain pin - indicates that the con?uration sequence is complete, and the startup sequence is in progress. cclk i/o con?uration clock for con?uring an fpga in sysconfig mode. busy i/o generally not used. after con?uration it is a user-programmable i/o pin. csn i sysconfig chip select (active low). during con?uration, a pull-up is enabled. after con?uration it is user a programmable i/o pin. cs1n i sysconfig chip select (active low). during con?uration, a pull-up is enabled. after con?uration it is user programmable i/o pin writen i write data on parallel port (active low). after con?uration it is a user pro- grammable i/o pin d[7:0] i/o sysconfig port data i/o. after con?uration these are user programmable i/o pins. dout, cson o output for serial con?uration data (rising edge of cclk) when using sysconfig port. after con?uration, it is a user-programmable i/o pin. di i input for serial con?uration data (clocked with cclk) when using syscon- fig port. during con?uration, a pull-up is enabled. after con?uration it is a user-programmable i/o pin. sleepn 2 i sleep mode pin - active low sleep pin. when this pin is held high, the device operates normally. when driven low, the device moves into sleep mode after a speci?d time.this pin has a weak internal pull-up, but when not used an external pull-up to v cc is recommended. toe 3 i test output enable tri-states all i/o pins when driven low. this pin has a weak internal pull-up, but when not used an external pull-up to v cc is recom- mended. 1. applies to lfxp10, LFXP15 and lfxp20 only. 2. applies to lfxp ? devices only. 3. applies to lfxp ? devices only. signal descriptions (cont.) signal name i/o descriptions
4-3 pinout information lattice semiconductor latticexp family data sheet pics and ddr data (dq) pins associated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic polarity ddr strobe (dqs) and data (dq) pins p[edge] [n-4] atruedq b complement dq p[edge] [n-3] atruedq b complement dq p[edge] [n-2] atruedq b complement dq p[edge] [n-1] atruedq p[edge] [n] b complement dq p[edge] [n+1] a true [edge]dqsn b complement dq p[edge] [n+2] atruedq b complement dq p[edge] [n+3] atruedq b complement dq notes: 1. ? is a row/column pic number. 2. the ddr interface is designed for memories that support one dqs strobe per eight bits of data. in some packages, all the pote ntial ddr data (dq) pins may not be available. 3. the de?ition of the pic numbering is provided in the signal names column of the signal descriptions table in this data sheet .
4-4 pinout information lattice semiconductor latticexp family data sheet pin information summary 1 xp3 xp6 pin type 100 tqfp 144 tqfp 208 pqfp 144 tqfp 208 pqfp 256 fpbga single ended user i/o 62 100 136 100 142 188 differential pair user i/o 2 19 35 56 35 58 80 con?uration dedicated 11 11 11 11 11 11 muxed 14 14 14 14 14 14 tap 555555 dedicated (total without supplies) 666666 v cc 248488 v ccaux 222224 v ccpll 222222 v ccio bank0 112122 bank1 112122 bank2 112122 bank3 112122 bank4 122222 bank5 112122 bank6 112122 bank7 112122 gnd 10 13 24 13 24 24 gnd pll 222222 nc 006000 single ended/differential i/o per bank 2 bank0 8/2 12/3 20/8 12/3 20/8 26/11 bank1 9/0 12/2 18/6 12/2 18/6 26/11 bank2 8/3 12/5 14/6 12/5 17/7 21/9 bank3 6/2 13/5 14/6 13/5 14/6 21/9 bank4 5/2 14/6 21/9 14/6 21/9 26/11 bank5 12/4 12/4 21/9 12/4 21/9 26/11 bank6 4/2 13/5 14/6 13/5 17/7 21/9 bank7 10/4 12/5 14/6 12/5 14/6 21/9 v ccj 111111 1. during con?uration the user-programmable i/os are tri-stated with an internal pull-up resistor enabled. if any pin is not u sed (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. 2. the differential i/o per bank includes both dedicated lvds and emulated lvds pin pairs. please see the logic signal connectio ns table for more information.
4-5 pinout information lattice semiconductor latticexp family data sheet pin information summary 1 (cont.) xp10 xp15 xp20 pin type 256 fpbga 388 fpbga 256 fpbga 388 fpbga 484 fpbga 256 fpbga 388 fpbga 484 fpbga single ended user i/o 188 244 188 268 300 188 268 340 differential pair user i/o 2 76 104 76 112 128 76 112 144 con?uration dedicated 11 11 11 11 11 11 11 11 muxed 14 14 14 14 14 14 14 14 tap 55555555 dedicated (total without supplies) 66666666 v cc 8148142881428 v ccaux 4444124412 v ccpll 22222222 v ccio bank0 25254254 bank1 25254254 bank2 24244244 bank3 24244244 bank4 25254254 bank5 25254254 bank6 24244244 bank7 24244244 gnd 24 50 24 50 56 24 50 56 gnd pll 22222222 nc 0240 0400 0 0 single ended/ differential i/o per bank 2 bank0 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank1 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank2 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 bank3 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 bank4 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank5 26/11 33/14 26/11 39/16 40/17 26/11 39/16 47/20 bank6 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 bank7 21/8 28/12 21/8 28/12 35/15 21/8 28/12 38/16 v ccj 11111111 1. during con?uration the user-programmable i/os are tri-stated with an internal pull-up resistor enabled. if any pin is not u sed (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. 2. the differential i/o per bank includes both dedicated lvds and emulated lvds pin pairs. please see the logic signal connectio ns table for more information.
4-6 pinout information lattice semiconductor latticexp family data sheet power supply and nc connections signals 100 tqfp 144 tqfp 208 pqfp 256 fpbga 388 fpbga 484 fpbga v cc 28, 77 14, 39, 73, 112 19, 35, 53, 80, 107, 151, 158, 182 d4, d13, e5, e12, m5, m12, n4, n13 h9, j8, j15, k8, k15, l8, l15, m8, m15, n8, n15, p8, p15, r9 f10, f13, g9, g10, g13, g14, h8, h15, j7, j16, k6, k7, k16, k17, n6, n7, n16, n17, p7, p16, r8, r15, t9, t10, t13, t14, u10, u13 v ccio0 94 133 189, 199 f7, f8 g8, g9, g10, g11, h8 f11, g11, h10, h11 v ccio1 82 119 167, 177 f9, f10 g12, g13, g14, g15, h15 f12, g12, h12, h13 v ccio2 65 98 140, 149 g11, h11 h16, j16, k16, l16 k15, l15, l16, l17 v ccio3 58 88 115, 125 j11, k11 m16, n16, p16, r16 m15, m16, m17, n15 v ccio4 47 61, 68 87, 97 l9, l10 r15, t12, t13, t14, t15 r12, r13, t12, u12 v ccio5 38 49 64, 74 l7, l8 r8, t8, t9, t10, t11 r10, r11, t11, u11 v ccio6 22 21 28, 41 j6, k6 m7, n7, p7, r7 m6, m7, m8, n8 v ccio7 7 8 13, 23 g6, h6 h7, j7, k7, l7 k8, l6, l7, l8 v ccj 73 108 154 d16 e20 e20 v ccp0 17 19 25 h4 m2 l5 v ccp1 60 91 128 j12 m21 l18 v ccaux 25, 71 36, 106 50, 152 e4, e13, m4, m13 g7, g16, t7, t16 g7, g8, g15, g16, h7, h16, r7, r16, t7, t8, t15, t16 gnd 1 10, 18, 21, 33, 43, 44, 52, 59, 68, 84, 90, 99 3, 11, 20, 28, 44, 54, 56, 64, 75, 85, 90, 101, 121, 127, 136 5, 7, 16, 26, 38, 47, 49, 59, 69, 79, 82, 92, 106, 109, 118, 121, 127, 130, 135, 143, 163, 172, 181, 184, 194, 207 a1, a16, f6, f11, g7, g8, g9, g10, h5, h7, h8, h9, h10, j7, j8, j9, j10, j13, k7, k8, k9, k10, l6, l11, t1, t16 a1, a22, h10, h11, h12, h13, h14, j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n1, n9, n10, n11, n12, n13, n14, n22, p9, p10, p11, p12, p13, p14, r10, r11, r12, r13, r14, ab1, ab22 a1, a2, a21, a22, b1, b22, h9, h14, j8, j9, j10, j11, j12, j13, j14, j15, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, m20, n2, n9, n10, n11, n12, n13, n14, p8, p9, p10, p11, p12, p13, p14, p15, r9, r14, aa1, aa22, ab1, ab2, ab21, ab22 nc 2 xp3: 27, 33, 34, 129, 133, 134 xp10: c2, c15, c16, c17, d4, d5, d6, d7, d16, d17, e4, e19, w3, w4, w7, w17, w18, w19, w20, y3, y15, y16, aa1, aa2 xp15: b21, c4, c5, c6, c18, c19, c20, c21, d6, d18, e4, e6, e18, f6, l1, l19, l20, m1, m2, m19, m21, n1, n21, n22, p1, p2, u5, u6, u17, u18, v5, v6, v17, v18, w17, w18, w19, y3, y4, y5 1. all grounds must be electrically connected at the board level. 2. nc pins should not be connected to any active signals, v cc or gnd.
4-7 pinout information lattice semiconductor latticexp family data sheet lfxp3 logic signal connections: 100 tqfp pin number pin function bank differential dual function 1 cfg1 0 - - 2 done 0 - - 3 programn 7 - - 4 cclk 7 - - 5 pl3a 7 t lum0_pllt_fb_a 6 pl3b 7 c lum0_pllc_fb_a 7 vccio7 7 - - 8 pl5a 7 - vref1_7 9 pl6b 7 - vref2_7 10 gndio7 7 - - 11 pl7a 7 t 3 dqs 12 pl7b 7 c 3 - 13 pl8a 7 t lum0_pllt_in_a 14 pl8b 7 c lum0_pllc_in_a 15 pl9a 7 t 3 - 16 pl9b 7 c 3 - 17 vccp0 - - - 18 gndp0 - - - 19 pl12a 6 t pclkt6_0 20 pl12b 6 c pclkc6_0 21 gndio6 6 - - 22 vccio6 6 - - 23 pl18a 6 t 3 - 24 pl18b 6 c 3 - 25 vccaux - - - 26 sleepn 1 /toe 2 --- 27 initn 5 - - 28 vcc - - - 29 pb2b 5 - vref1_5 30 pb5b 5 - vref2_5 31 pb8a 5 t - 32 pb8b 5 c - 33 gndio5 5 - - 34 pb9a 5 - - 35 pb10b 5 - - 36 pb11a 5 t dqs 37 pb11b 5 c - 38 vccio5 5 - - 39 pb12a 5 t - 40 pb12b 5 c - 41 pb13a 5 t - 42 pb13b 5 c - 43 gnd - - -
4-8 pinout information lattice semiconductor latticexp family data sheet 44 gndio4 4 - - 45 pb15a 4 t pclkt4_0 46 pb15b 4 c pclkc4_0 47 vccio4 4 - - 48 pb19a 4 t dqs 49 pb19b 4 c vref1_4 50 pb24a 4 - vref2_4 51 pr18b 3 c 3 - 52 gndio3 3 - - 53 pr18a 3 t 3 - 54 pr15b 3 - vref1_3 55 pr14a 3 - vref2_3 56 pr13b 3 c - 57 pr13a 3 t - 58 vccio3 3 - - 59 gndp1 - - - 60 vccp1 - - - 61 pr9b 2 c pclkc2_0 62 pr9a 2 t pclkt2_0 63 pr8b 2 c rum0_pllc_in_a 64 pr8a 2 t rum0_pllt_in_a 65 vccio2 2 - - 66 pr6b 2 - vref1_2 67 pr5a 2 - vref2_2 68 gndio2 2 - - 69 pr3b 2 c rum0_pllc_fb_a 70 pr3a 2 t rum0_pllt_fb_a 71 vccaux - - - 72 tdo - - - 73 vccj - - - 74 tdi - - - 75 tms - - - 76 tck - - - 77 vcc - - - 78 pt24a 1 - - 79 pt23a 1 - d0 80 pt22b 1 - d1 81 pt21a 1 - d2 82 vccio1 1 - - 83 pt20b 1 - d3 84 gndio1 1 - - 85 pt17a 1 - d4 86 pt16a 1 - d5 87 pt15b 1 - d6 lfxp3 logic signal connections: 100 tqfp (cont.) pin number pin function bank differential dual function
4-9 pinout information lattice semiconductor latticexp family data sheet 88 pt14b 1 - d7 89 pt13b 0 c busy 90 gndio0 0 - - 91 pt13a 0 t cs1n 92 pt12b 0 c pclkc0_0 93 pt12a 0 t pclkt0_0 94 vccio0 0 - - 95 pt9a 0 - dout 96 pt8a 0 - writen 97 pt6a 0 - di 98 pt5a 0 - csn 99 gnd - - - 100 cfg0 0 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp3 logic signal connections: 100 tqfp (cont.) pin number pin function bank differential dual function
4-10 pinout information lattice semiconductor latticexp family data sheet lfxp3 & lfxp6 logic signal connections: 144 tqfp pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function 1 programn 7 - - programn 7 - - 2 cclk 7 - - cclk 7 - - 3 gnd - - - gnd - -- 4 pl2a 7 t 3 - pl2a 7 t 3 - 5 pl2b 7 c 3 - pl2b 7 c 3 - 6 pl3a 7 t lum0_pllt_fb_a pl3a 7 t lum0_pllt_fb_a 7 pl3b 7 c lum0_pllc_fb_a pl3b 7 c lum0_pllc_fb_a 8 vccio7 7 - - vccio7 7 - - 9 pl5a 7 - vref1_7 pl5a 7 - vref1_7 10 pl6b 7 - vref2_7 pl6b 7 - vref2_7 11 gndio7 7 - - gndio7 7 - - 12 pl7a 7 t 3 dqs pl7a 7 t 3 dqs 13 pl7b 7 c 3 - pl7b 7 c 3 - 14 vcc - - - vcc - -- 15 pl8a 7 t lum0_pllt_in_a pl8a 7 t lum0_pllt_in_a 16 pl8b 7 c lum0_pllc_in_a pl8b 7 c lum0_pllc_in_a 17 pl9a 7 t 3 - pl9a 7 t 3 - 18 pl9b 7 c 3 - pl9b 7 c 3 - 19 vccp0 - - - vccp0 - - - 20 gndp0 - - - gndp0 - - - 21 vccio6 6 - - vccio6 6 - - 22 pl11a 6 t 3 - pl16a 6 t 3 - 23 pl11b 6 c 3 - pl16b 6 c 3 - 24 pl12a 6 t pclkt6_0 pl17a 6 t pclkt6_0 25 pl12b 6 c pclkc6_0 pl17b 6 c pclkc6_0 26 pl13a 6 t 3 - pl18a 6 t 3 - 27 pl13b 6 c 3 - pl18b 6 c 3 - 28 gndio6 6 - - gndio6 6 - - 29 pl14a 6 - vref1_6 pl22a 6 - vref1_6 30 pl15b 6 - vref2_6 pl23b 6 - vref2_6 31 pl16a 6 t 3 dqs pl24a 6 t 3 dqs 32 pl16b 6 c 3 - pl24b 6 c 3 - 33 pl17a 6 - - pl25a 6 - - 34 pl18a 6 t 3 - pl26a 6 t 3 - 35 pl18b 6 c 3 - pl26b 6 c 3 - 36 vccaux - - - vccaux - -- 37 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - 38 initn 5 - - initn 5 - - 39 vcc - - - vcc - -- 40 pb2b 5 - vref1_5 pb5b 5 - vref1_5 41 pb5b 5 - vref2_5 pb8b 5 - vref2_5 42 pb7a 5 t - pb10a 5 t - 43 pb7b 5 c - pb10b 5 c - 44 gndio5 5 - - gndio5 5 - - 45 pb9a 5 - - pb12a 5 - - 46 pb10b 5 - - pb13b 5 - -
4-11 pinout information lattice semiconductor latticexp family data sheet 47 pb11a 5 t dqs pb14a 5 t dqs 48 pb11b 5 c - pb14b 5 c - 49 vccio5 5 - - vccio5 5 - - 50 pb12a 5 t - pb15a 5 t - 51 pb12b 5 c - pb15b 5 c - 52 pb13a 5 t - pb16a 5 t - 53 pb13b 5 c - pb16b 5 c - 54 gnd - - - gnd - -- 55 pb14a 4 t - pb17a 4 t - 56 gndio4 4 - - gndio4 4 - - 57 pb14b 4 c - pb17b 4 c - 58 pb15a 4 t pclkt4_0 pb18a 4 t pclkt4_0 59 pb15b 4 c pclkc4_0 pb18b 4 c pclkc4_0 60 pb16a 4 t - pb19a 4 t - 61 vccio4 4 - - vccio4 4 - - 62 pb16b 4 c - pb19b 4 c - 63 pb19a 4 t dqs pb22a 4 t dqs 64 gndio4 4 - - gndio4 4 - - 65 pb19b 4 c vref1_4 pb22b 4 c vref1_4 66 pb20a 4 t - pb23a 4 t - 67 pb20b 4 c - pb23b 4 c - 68 vccio4 4 - - vccio4 4 - - 69 pb22a 4 - - pb25a 4 - - 70 pb24a 4 t vref2_4 pb27a 4 t vref2_4 71 pb24b 4 c - pb27b 4 c - 72 pb25a 4 - - pb28a 4 - - 73 vcc - - - vcc - -- 74 pr18b 3 c 3 - pr26b 3 c 3 - 75 gndio3 3 - - gndio3 3 - - 76 pr18a 3 t 3 - pr26a 3 t 3 - 77 pr17b 3 c - pr25b 3 c - 78 pr17a 3 t - pr25a 3 t - 79 pr16b 3 c 3 - pr24b 3 c 3 - 80 pr16a 3 t 3 dqs pr24a 3 t 3 dqs 81 pr15b 3 - vref1_3 pr23b 3 - vref1_3 82 pr14a 3 - vref2_3 pr22a 3 - vref2_3 83 pr13b 3 c - pr21b 3 c 3 - 84 pr13a 3 t - pr21a 3 t 3 - 85 gnd - - - gnd - -- 86 pr12a 3 - - pr20a 3 - - 87 pr11b 3 c - pr19b 3 c 3 - 88 vccio3 3 - - vccio3 3 - - 89 pr11a 3 t - pr19a 3 t 3 - 90 gndp1 - - - gndp1 - - - 91 vccp1 - - - vccp1 - - - 92 pr9b 2 c pclkc2_0 pr12b 2 c pclkc2_0 lfxp3 & lfxp6 logic signal connections: 144 tqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-12 pinout information lattice semiconductor latticexp family data sheet 93 pr9a 2 t pclkt2_0 pr12a 2 t pclkt2_0 94 pr8b 2 c rum0_pllc_in_a pr8b 2 c rum0_pllc_in_a 95 pr8a 2 t rum0_pllt_in_a pr8a 2 t rum0_pllt_in_a 96 pr7b 2 c 3 - pr7b 2 c 3 - 97 pr7a 2 t 3 dqs pr7a 2 t 3 dqs 98 vccio2 2 - - vccio2 2 - - 99 pr6b 2 - vref1_2 pr6b 2 - vref1_2 100 pr5a 2 - vref2_2 pr5a 2 - vref2_2 101 gndio2 2 - - gndio2 2 - - 102 pr3b 2 c rum0_pllc_fb_a pr3b 2 c rum0_pllc_fb_a 103 pr3a 2 t rum0_pllt_fb_a pr3a 2 t rum0_pllt_fb_a 104 pr2b 2 c 3 - pr2b 2 c 3 - 105 pr2a 2 t 3 - pr2a 2 t 3 - 106 vccaux - - - vccaux - -- 107 tdo - - - tdo - - - 108 vccj - - - vccj - -- 109 tdi - - - tdi - -- 110 tms - - - tms - -- 111 tck - - - tck - -- 112 vcc - - - vcc - -- 113 pt25a 1 - vref1_1 pt28a 1 - vref1_1 114 pt24a 1 - - pt27a 1 - - 115 pt23a 1 - d0 pt26a 1 - d0 116 pt22b 1 c d1 pt25b 1 c d1 117 pt22a 1 t vref2_1 pt25a 1 t vref2_1 118 pt21a 1 - d2 pt24a 1 - d2 119 vccio1 1 - - vccio1 1 - - 120 pt20b 1 - d3 pt23b 1 - d3 121 gndio1 1 - - gndio1 1 - - 122 pt17a 1 - d4 pt20a 1 - d4 123 pt16a 1 - d5 pt19a 1 - d5 124 pt15b 1 c d6 pt18b 1 c d6 125 pt15a 1 t - pt18a 1 t - 126 pt14b 1 - d7 pt17b 1 - d7 127 gnd - - - gnd - -- 128 pt13b 0 c busy pt16b 0 c busy 129 pt13a 0 t cs1n pt16a 0 t cs1n 130 pt12b 0 c pclkc0_0 pt15b 0 c pclkc0_0 131 pt12a 0 t pclkt0_0 pt15a 0 t pclkt0_0 132 pt11b 0 c - pt14b 0 c - 133 vccio0 0 - - vccio0 0 - - 134 pt11a 0 t dqs pt14a 0 t dqs 135 pt9a 0 - dout pt12a 0 - dout 136 gndio0 0 - - gndio0 0 - - 137 pt8a 0 - writen pt11a 0 - writen 138 pt7a 0 - vref1_0 pt10a 0 - vref1_0 lfxp3 & lfxp6 logic signal connections: 144 tqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-13 pinout information lattice semiconductor latticexp family data sheet 139 pt6a 0 - di pt9a 0 - di 140 pt5a 0 - csn pt8a 0 - csn 141 pt3b 0 - vref2_0 pt6b 0 - vref2_0 142 cfg0 0 - - cfg0 0 - - 143 cfg1 0 - - cfg1 0 - - 144 done 0 - - done 0 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp3 & lfxp6 logic signal connections: 144 tqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-14 pinout information lattice semiconductor latticexp family data sheet lfxp3 & lfxp6 logic signal connections: 208 pqfp pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function 1 cfg1 0 - - cfg1 0 - - 2 done 0 - - done 0 - - 3 programn 7 - - programn 7 - - 4 cclk 7 - - cclk 7 - - 5 gnd - - - gnd - -- 6 pl2a 7 t 3 - pl2a 7 t 3 - 7 gndio7 7 - - gndio7 7 - - 8 pl2b 7 c 3 - pl2b 7 c 3 - 9 pl3a 7 t lum0_pllt_fb_a pl3a 7 t lum0_pllt_fb_a 10 pl3b 7 c lum0_pllc_fb_a pl3b 7 c lum0_pllc_fb_a 11 pl4a 7 t 3 - pl4a 7 t 3 - 12 pl4b 7 c 3 - pl4b 7 c 3 - 13 vccio7 7 - - vccio7 7 - - 14 pl5a 7 - vref1_7 pl5a 7 - vref1_7 15 pl6b 7 - vref2_7 pl6b 7 - vref2_7 16 gndio7 7 - - gndio7 7 - - 17 pl7a 7 t 3 dqs pl7a 7 t 3 dqs 18 pl7b 7 c 3 - pl7b 7 c 3 - 19 vcc - - - vcc - -- 20 pl8a 7 t lum0_pllt_in_a pl8a 7 t lum0_pllt_in_a 21 pl8b 7 c lum0_pllc_in_a pl8b 7 c lum0_pllc_in_a 22 pl9a 7 t 3 - pl9a 7 t 3 - 23 vccio7 7 - - vccio7 7 - - 24 pl9b 7 c 3 - pl9b 7 c 3 - 25 vccp0 - - - vccp0 - - - 26 gndp0 - - - gndp0 - - - 27 nc - - - pl15b 6 - - 28 vccio6 6 - - vccio6 6 - - 29 pl11a 6 t 3 - pl16a 6 t 3 - 30 pl11b 6 c 3 - pl16b 6 c 3 - 31 pl12a 6 t pclkt6_0 pl17a 6 t pclkt6_0 32 pl12b 6 c pclkc6_0 pl17b 6 c pclkc6_0 33 nc - - - pl18a 6 t 3 - 34 nc - - - pl18b 6 c 3 - 35 vcc - - - vcc - -- 36 pl13a 6 t 3 - pl21a 6 t 3 - 37 pl13b 6 c 3 - pl21b 6 c 3 - 38 gndio6 6 - - gndio6 6 - - 39 pl14a 6 - vref1_6 pl22a 6 - vref1_6 40 pl15b 6 - vref2_6 pl23b 6 - vref2_6 41 vccio6 6 - - vccio6 6 - - 42 pl16a 6 t 3 dqs pl24a 6 t 3 dqs 43 pl16b 6 c 3 - pl24b 6 c 3 - 44 pl17a 6 t - pl25a 6 t - 45 pl17b 6 c - pl25b 6 c - 46 pl18a 6 t 3 - pl26a 6 t 3 -
4-15 pinout information lattice semiconductor latticexp family data sheet 47 gndio6 6 - - gndio6 6 - - 48 pl18b 6 c 3 - pl26b 6 c 3 - 49 gnd - - - gnd - -- 50 vccaux - - - vccaux - -- 51 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - 52 initn 5 - - initn 5 - - 53 vcc - - - vcc - -- 54 pb2b 5 - vref1_5 pb5b 5 - vref1_5 55 pb3a 5 t - pb6a 5 t dqs 56 pb3b 5 c - pb6b 5 c - 57 pb4a 5 t - pb7a 5 t - 58 pb4b 5 c - pb7b 5 c - 59 gndio5 5 - - gndio5 5 - - 60 pb5a 5 t - pb8a 5 t - 61 pb5b 5 c vref2_5 pb8b 5 c vref2_5 62 pb6a 5 t - pb9a 5 t - 63 pb6b 5 c - pb9b 5 c - 64 vccio5 5 - - vccio5 5 - - 65 pb7a 5 t - pb10a 5 t - 66 pb7b 5 c - pb10b 5 c - 67 pb8a 5 t - pb11a 5 t - 68 pb8b 5 c - pb11b 5 c - 69 gndio5 5 - - gndio5 5 - - 70 pb9a 5 - - pb12a 5 - - 71 pb10b 5 - - pb13b 5 - - 72 pb11a 5 t dqs pb14a 5 t dqs 73 pb11b 5 c - pb14b 5 c - 74 vccio5 5 - - vccio5 5 - - 75 pb12a 5 t - pb15a 5 t - 76 pb12b 5 c - pb15b 5 c - 77 pb13a 5 t - pb16a 5 t - 78 pb13b 5 c - pb16b 5 c - 79 gnd - - - gnd - -- 80 vcc - - - vcc - -- 81 pb14a 4 t - pb17a 4 t - 82 gndio4 4 - - gndio4 4 - - 83 pb14b 4 c - pb17b 4 c - 84 pb15a 4 t pclkt4_0 pb18a 4 t pclkt4_0 85 pb15b 4 c pclkc4_0 pb18b 4 c pclkc4_0 86 pb16a 4 t - pb19a 4 t - 87 vccio4 4 - - vccio4 4 - - 88 pb16b 4 c - pb19b 4 c - 89 pb17a 4 - - pb20a 4 - - 90 pb18b 4 - - pb21b 4 - - 91 pb19a 4 t dqs pb22a 4 t dqs 92 gndio4 4 - - gndio4 4 - - lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-16 pinout information lattice semiconductor latticexp family data sheet 93 pb19b 4 c vref1_4 pb22b 4 c vref1_4 94 pb20a 4 t - pb23a 4 t - 95 pb20b 4 c - pb23b 4 c - 96 pb21a 4 t - pb24a 4 t - 97 vccio4 4 - - vccio4 4 - - 98 pb21b 4 c - pb24b 4 c - 99 pb22a 4 t - pb25a 4 t - 100 pb22b 4 c - pb25b 4 c - 101 pb23a 4 t - pb26a 4 t - 102 pb23b 4 c - pb26b 4 c - 103 pb24a 4 t vref2_4 pb27a 4 - vref2_4 104 pb24b 4 c - pb30a 4 t dqs 105 pb25a 4 - - pb30b 4 c - 106 gnd - - - gnd - -- 107 vcc - - - vcc - -- 108 pr18b 3 c 3 - pr26b 3 c 3 - 109 gndio3 3 - - gndio3 3 - - 110 pr18a 3 t 3 - pr26a 3 t 3 - 111 pr17b 3 c - pr25b 3 c - 112 pr17a 3 t - pr25a 3 t - 113 pr16b 3 c 3 - pr24b 3 c 3 - 114 pr16a 3 t 3 dqs pr24a 3 t 3 dqs 115 vccio3 3 - - vccio3 3 - - 116 pr15b 3 - vref1_3 pr23b 3 - vref1_3 117 pr14a 3 - vref2_3 pr22a 3 - vref2_3 118 gndio3 3 - - gndio3 3 - - 119 pr13b 3 c - pr21b 3 c 3 - 120 pr13a 3 t - pr21a 3 t 3 - 121 gnd - - - gnd - -- 122 pr12b 3 c - pr20b 3 c - 123 pr12a 3 t - pr20a 3 t - 124 pr11b 3 c - pr19b 3 c 3 - 125 vccio3 3 - - vccio3 3 - - 126 pr11a 3 t - pr19a 3 t 3 - 127 gndp1 - - - gndp1 - - - 128 vccp1 - - - vccp1 - - - 129 nc - - - pr13a 2 - - 130 gnd - - - gnd - -- 131 pr9b 2 c pclkc2_0 pr12b 2 c pclkc2_0 132 pr9a 2 t pclkt2_0 pr12a 2 t pclkt2_0 133 nc - - - pr11b 2 c 3 - 134 nc - - - pr11a 2 t 3 - 135 gndio2 2 - - gndio2 2 - - 136 pr8b 2 c rum0_pllc_in_a pr8b 2 c rum0_pllc_in_a 137 pr8a 2 t rum0_pllt_in_a pr8a 2 t rum0_pllt_in_a 138 pr7b 2 c 3 - pr7b 2 c 3 - lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-17 pinout information lattice semiconductor latticexp family data sheet 139 pr7a 2 t 3 dqs pr7a 2 t 3 dqs 140 vccio2 2 - - vccio2 2 - - 141 pr6b 2 - vref1_2 pr6b 2 - vref1_2 142 pr5a 2 - vref2_2 pr5a 2 - vref2_2 143 gndio2 2 - - gndio2 2 - - 144 pr4b 2 c 3 - pr4b 2 c 3 - 145 pr4a 2 t 3 - pr4a 2 t 3 - 146 pr3b 2 c rum0_pllc_fb_a pr3b 2 c rum0_pllc_fb_a 147 pr3a 2 t rum0_pllt_fb_a pr3a 2 t rum0_pllt_fb_a 148 pr2b 2 c 3 - pr2b 2 c 3 - 149 vccio2 2 - - vccio2 2 - - 150 pr2a 2 t 3 - pr2a 2 t 3 - 151 vcc - - - vcc - -- 152 vccaux - - - vccaux - -- 153 tdo - - - tdo - - - 154 vccj - - - vccj - -- 155 tdi - - - tdi - -- 156 tms - - - tms - -- 157 tck - - - tck - -- 158 vcc - - - vcc - -- 159 pt25a 1 - vref1_1 pt28a 1 - vref1_1 160 pt24b 1 c - pt27b 1 c - 161 pt24a 1 t - pt27a 1 t - 162 pt23a 1 - d0 pt26a 1 - d0 163 gndio1 1 - - gndio1 1 - - 164 pt22b 1 c d1 pt25b 1 c d1 165 pt22a 1 t vref2_1 pt25a 1 t vref2_1 166 pt21a 1 - d2 pt24a 1 - d2 167 vccio1 1 - - vccio1 1 - - 168 pt20b 1 c d3 pt23b 1 c d3 169 pt20a 1 t - pt23a 1 t - 170 pt19b 1 c - pt22b 1 c - 171 pt19a 1 t dqs pt22a 1 t dqs 172 gndio1 1 - - gndio1 1 - - 173 pt18b 1 - - pt21b 1 - - 174 pt17a 1 - d4 pt20a 1 - d4 175 pt16b 1 c - pt19b 1 c - 176 pt16a 1 t d5 pt19a 1 t d5 177 vccio1 1 - - vccio1 1 - - 178 pt15b 1 c d6 pt18b 1 c d6 179 pt15a 1 t - pt18a 1 t - 180 pt14b 1 - d7 pt17b 1 - d7 181 gnd - - - gnd - -- 182 vcc - - - vcc - -- 183 pt13b 0 c busy pt16b 0 c busy 184 gndio0 0 - - gndio0 0 - - lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-18 pinout information lattice semiconductor latticexp family data sheet 185 pt13a 0 t cs1n pt16a 0 t cs1n 186 pt12b 0 c pclkc0_0 pt15b 0 c pclkc0_0 187 pt12a 0 t pclkt0_0 pt15a 0 t pclkt0_0 188 pt11b 0 c - pt14b 0 c - 189 vccio0 0 - - vccio0 0 - - 190 pt11a 0 t dqs pt14a 0 t dqs 191 pt10b 0 - - pt13b 0 - - 192 pt9a 0 - dout pt12a 0 - dout 193 pt8b 0 c - pt11b 0 c - 194 gndio0 0 - - gndio0 0 - - 195 pt8a 0 t writen pt11a 0 t writen 196 pt7b 0 c - pt10b 0 c - 197 pt7a 0 t vref1_0 pt10a 0 t vref1_0 198 pt6b 0 c - pt9b 0 c - 199 vccio0 0 - - vccio0 0 - - 200 pt6a 0 t di pt9a 0 t di 201 pt5b 0 c - pt8b 0 c - 202 pt5a 0 t csn pt8a 0 t csn 203 pt4b 0 c - pt7b 0 c - 204 pt4a 0 t - pt7a 0 t - 205 pt3b 0 - vref2_0 pt6b 0 - vref2_0 206 pt2b 0 - - pt5b 0 - - 207 gnd - - - gnd - -- 208 cfg0 0 - - cfg0 0 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp3 & lfxp6 logic signal connections: 208 pqfp (cont.) pin number lfxp3 lfxp6 pin function bank differential dual function pin function bank differential dual function
4-19 pinout information lattice semiconductor latticexp family data sheet lfxp6 & lfxp10 logic signal connections: 256 fpbga ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function c2 programn 7 - - programn 7 - - c1 cclk 7 - - cclk 7 - - - gndio7 7 - - gndio7 7 - - d2 pl3a 7 t lum0_pllt_fb_a pl3a 7 t lum0_pllt_fb_a d3 pl3b 7 c lum0_pllc_fb_a pl3b 7 c lum0_pllc_fb_a d1 pl2a 7 t 3 - pl5a 7 - - e2 pl5a 7 - vref1_7 pl6b 7 - vref1_7 - gndio7 7 - - gndio7 7 - - e1 pl7a 7 t 3 dqs pl7a 7 t 3 dqs f1 pl7b 7 c 3 - pl7b 7 c 3 - e3 pl12a 7 t - pl8a 7 t - f4 pl12b 7 c - pl8b 7 c - f3 pl4a 7 t 3 - pl9a 7 t 3 - f2 pl4b 7 c 3 - pl9b 7 c 3 - - gndio7 7 - - gndio7 7 - - g1 pl2b 7 c 3 - pl11b 7 - - g3 pl8a 7 t lum0_pllt_in_a pl12a 7 t lum0_pllt_in_a g2 pl8b 7 c lum0_pllc_in_a pl12b 7 c lum0_pllc_in_a h1 pl9a 7 t 3 - pl13a 7 t 3 - h2 pl9b 7 c 3 - pl13b 7 c 3 - g4 pl6b 7 - vref2_7 pl14a 7 - vref2_7 g5 pl14a 7 - - pl15b 7 - - - gndio7 7 - - gndio7 7 - - j1 pl11a 7 t 3 - pl16a 7 t 3 dqs j2 pl11b 7 c 3 - pl16b 7 c 3 - h3 pl13a 7 t 3 - pl18a 7 t 3 - j3 pl13b 7 c 3 - pl18b 7 c 3 - h4 vccp0 - - - vccp0 - - - h5 gndp0 - - - gndp0 - - - k1 pl17a 6 t pclkt6_0 pl20a 6 t pclkt6_0 k2 pl17b 6 c pclkc6_0 pl20b 6 c pclkc6_0 - gndio6 6 - - gndio6 6 - - j4 pl15b 6 - - pl22a 6 - - j5 pl22a 6 - vref1_6 pl23b 6 - vref1_6 l1 pl16a 6 t 3 - pl24a 6 t 3 dqs l2 pl16b 6 c 3 - pl24b 6 c 3 - m1 pl18a 6 t 3 - pl25a 6 t llm0_pllt_in_a m2 pl18b 6 c 3 - pl25b 6 c llm0_pllc_in_a k3 pl19a 6 t 3 - pl26a 6 t 3 - - gndio6 6 - - gndio6 6 - - l3 pl19b 6 c 3 - pl26b 6 c 3 - l4 pl21a 6 t 3 - pl28a 6 - -
4-20 pinout information lattice semiconductor latticexp family data sheet k4 pl20a 6 t - pl29a 6 t - k5 pl20b 6 c - pl29b 6 c - - gndio6 6 - - gndio6 6 - - n1 pl23b 6 - vref2_6 pl31a 6 - vref2_6 n2 pl21b 6 c 3 - pl32b 6 - - p1 pl24a 6 t 3 dqs pl33a 6 t 3 dqs p2 pl24b 6 c 3 - pl33b 6 c 3 - l5 pl25a 6 t - pl34a 6 t llm0_pllt_fb_a m6 pl25b 6 c - pl34b 6 c llm0_pllc_fb_a m3 pl26a 6 t 3 - pl35a 6 t 3 - - gndio6 6 - - gndio6 6 - - n3 pl26b 6 c 3 - pl35b 6 c 3 - p4 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - p3 initn 5 - - initn 5 - - - gndio5 5 - - gndio5 5 - - r4 pb2a 5 t - pb6a 5 t - n5 pb2b 5 c - pb6b 5 c - - gndio5 5 - - gndio5 5 - - p5 pb5b 5 - vref1_5 pb7a 5 t vref1_5 r1 pb3b 5 c - pb7b 5 c - n6 pb4a 5 - - pb8a 5 - - m7 pb3a 5 t - pb9b 5 - - r2 pb6a 5 t dqs pb10a 5 t dqs t2 pb6b 5 c - pb10b 5 c - r3 pb7a 5 t - pb11a 5 t - t3 pb7b 5 c - pb11b 5 c - - gndio5 5 - - gndio5 5 - - t4 pb8a 5 t - pb12a 5 t - r5 pb8b 5 c vref2_5 pb12b 5 c vref2_5 n7 pb9a 5 t - pb13a 5 t - m8 pb9b 5 c - pb13b 5 c - t5 pb10a 5 t - pb14a 5 t - p6 pb10b 5 c - pb14b 5 c - t6 pb11a 5 t - pb15a 5 t - r6 pb11b 5 c - pb15b 5 c - - gndio5 5 - - gndio5 5 - - p7 pb12a 5 - - pb16a 5 - - n8 pb13b 5 - - pb17b 5 - - r7 pb14a 5 t dqs pb18a 5 t dqs t7 pb14b 5 c - pb18b 5 c - p8 pb15a 5 t - pb19a 5 t - t8 pb15b 5 c - pb19b 5 c - lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-21 pinout information lattice semiconductor latticexp family data sheet r8 pb16a 5 t - pb20a 5 t - t9 pb16b 5 c - pb20b 5 c - r9 pb17a 4 t - pb21a 4 t - - gndio4 4 - - gndio4 4 - - p9 pb17b 4 c - pb21b 4 c - t10 pb18a 4 t pclkt4_0 pb22a 4 t pclkt4_0 t11 pb18b 4 c pclkc4_0 pb22b 4 c pclkc4_0 r10 pb19a 4 t - pb23a 4 t - p10 pb19b 4 c - pb23b 4 c - n9 pb20a 4 - - pb24a 4 - - m9 pb21b 4 - - pb25b 4 - - r12 pb22a 4 t dqs pb26a 4 t dqs - gndio4 4 - - gndio4 4 - - t12 pb22b 4 c vref1_4 pb26b 4 c vref1_4 p13 pb23a 4 t - pb27a 4 t - r13 pb23b 4 c - pb27b 4 c - m11 pb24a 4 t - pb28a 4 t - n11 pb24b 4 c - pb28b 4 c - n10 pb25a 4 t - pb29a 4 t - m10 pb25b 4 c - pb29b 4 c - t13 pb26a 4 t - pb30a 4 t - - gndio4 4 - - gndio4 4 - - p14 pb26b 4 c - pb30b 4 c - r11 pb27a 4 t vref2_4 pb31a 4 t vref2_4 p12 pb27b 4 c - pb31b 4 c - t14 pb28a 4 - - pb32a 4 - - r14 pb29b 4 - - pb33b 4 - - p11 pb30a 4 t dqs pb34a 4 t dqs n12 pb30b 4 c - pb34b 4 c - t15 pb31a 4 t - pb35a 4 t - - gndio4 4 - - gndio4 4 - - r15 pb31b 4 c - pb35b 4 c - - gndio3 3 - - gndio3 3 - - p15 pr26b 3 c 3 - pr34b 3 c rlm0_pllc_fb_a n15 pr26a 3 t 3 - pr34a 3 t rlm0_pllt_fb_a p16 pr24b 3 c 3 - pr33b 3 c 3 - r16 pr24a 3 t 3 dqs pr33a 3 t 3 dqs m15 pr15b 3 - - pr32b 3 - - n14 pr23b 3 - vref1_3 pr31a 3 - vref1_3 - gndio3 3 - - gndio3 3 - - m14 pr25b 3 c - pr29b 3 c - l13 pr25a 3 t - pr29a 3 t - lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-22 pinout information lattice semiconductor latticexp family data sheet l15 pr21b 3 c 3 - pr28b 3 c 3 - l14 pr21a 3 t 3 - pr28a 3 t 3 - - gndio3 3 - - gndio3 3 - - l12 pr17b 3 c - pr26a 3 - - m16 pr20b 3 c - pr25b 3 c rlm0_pllc_in_a n16 pr20a 3 t - pr25a 3 t rlm0_pllt_in_a k14 pr19b 3 c 3 - pr24b 3 c 3 - k15 pr19a 3 t 3 - pr24a 3 t 3 dqs k12 pr17a 3 t - pr23b 3 - - k13 pr22a 3 - vref2_3 pr22a 3 - vref2_3 - gndio3 3 - - gndio3 3 - - l16 pr18b 3 c 3 - pr21b 3 c 3 - k16 pr18a 3 t 3 - pr21a 3 t 3 - j15 pr16b 3 c 3 - pr19b 3 c 3 - j14 pr16a 3 t 3 - pr19a 3 t 3 - j13 gndp1 - - - gndp1 - - - j12 vccp1 - - - vccp1 - - - - gndio2 2 - - gndio2 2 - - j16 pr12b 2 c pclkc2_0 pr17b 2 c pclkc2_0 h16 pr12a 2 t pclkt2_0 pr17a 2 t pclkt2_0 h13 pr13b 2 c 3 - pr16b 2 c 3 - h12 pr13a 2 t 3 - pr16a 2 t 3 dqs h15 pr2b 2 c 3 - pr15b 2 - - h14 pr6b 2 - vref1_2 pr14a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - g15 pr11b 2 c 3 - pr13b 2 c 3 - g14 pr11a 2 t 3 - pr13a 2 t 3 - g16 pr8b 2 c rum0_pllc_in_a pr12b 2 c rum0_pllc_in_a f16 pr8a 2 t rum0_pllt_in_a pr12a 2 t rum0_pllt_in_a g13 pr2a 2 t 3 - pr11b 2 - - - gndio2 2 - - gndio2 2 - - g12 pr9b 2 c 3 - pr8b 2 c - f13 pr9a 2 t 3 - pr8a 2 t - b16 pr7b 2 c 3 - pr7b 2 c 3 - c16 pr7a 2 t 3 dqs pr7a 2 t 3 dqs f15 pr14a 2 - - pr6b 2 - - e15 pr5a 2 - vref2_2 pr5a 2 - vref2_2 - gndio2 2 - - gndio2 2 - - f14 pr4b 2 c 3 - pr4b 2 c 3 - e14 pr4a 2 t 3 - pr4a 2 t 3 - d15 pr3b 2 c rum0_pllc_fb_a pr3b 2 c rum0_pllc_fb_a c15 pr3a 2 t rum0_pllt_fb_a pr3a 2 t rum0_pllt_fb_a lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-23 pinout information lattice semiconductor latticexp family data sheet e16 tdo - - - tdo - - - d16 vccj - - - vccj - - - d14 tdi - - - tdi - - - c14 tms - - - tms - - - b14 tck - - - tck - - - - gndio1 1 - - gndio1 1 - - a15 pt31b 1 c - pt35b 1 c - b15 pt31a 1 t - pt35a 1 t - - gndio1 1 - - gndio1 1 - - d12 pt28a 1 - vref1_1 pt34b 1 c vref1_1 c11 pt30a 1 t dqs pt34a 1 t dqs a14 pt29b 1 - - pt33b 1 - - b13 pt30b 1 c - pt32a 1 - - f12 pt27b 1 c - pt31b 1 c - e11 pt27a 1 t - pt31a 1 t - a13 pt26b 1 c - pt30b 1 c - c13 pt26a 1 t d0 pt30a 1 t d0 - gndio1 1 - - gndio1 1 - - c10 pt25b 1 c d1 pt29b 1 c d1 e10 pt25a 1 t vref2_1 pt29a 1 t vref2_1 a12 pt24b 1 c - pt28b 1 c - b12 pt24a 1 t d2 pt28a 1 t d2 c12 pt23b 1 c d3 pt27b 1 c d3 a11 pt23a 1 t - pt27a 1 t - b11 pt22b 1 c - pt26b 1 c - d11 pt22a 1 t dqs pt26a 1 t dqs - gndio1 1 - - gndio1 1 - - b9 pt21b 1 - - pt25b 1 - - d9 pt20a 1 - d4 pt24a 1 - d4 a10 pt19b 1 c - pt23b 1 c - b10 pt19a 1 t d5 pt23a 1 t d5 d10 pt18b 1 c d6 pt22b 1 c d6 a9 pt18a 1 t - pt22a 1 t - c9 pt17b 1 c d7 pt21b 1 c d7 c8 pt17a 1 t - pt21a 1 t - e9 pt16b 0 c busy pt20b 0 c busy - gndio0 0 - - gndio0 0 - - b8 pt16a 0 t cs1n pt20a 0 t cs1n a8 pt15b 0 c pclkc0_0 pt19b 0 c pclkc0_0 a7 pt15a 0 t pclkt0_0 pt19a 0 t pclkt0_0 b7 pt14b 0 c - pt18b 0 c - c7 pt14a 0 t dqs pt18a 0 t dqs lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-24 pinout information lattice semiconductor latticexp family data sheet e8 pt13b 0 - - pt17b 0 - - d8 pt12a 0 - dout pt16a 0 - dout a6 pt11b 0 c - pt15b 0 c - - gndio0 0 - - gndio0 0 - - c6 pt11a 0 t writen pt15a 0 t writen e7 pt10b 0 c - pt14b 0 c - d7 pt10a 0 t vref1_0 pt14a 0 t vref1_0 a5 pt9b 0 c - pt13b 0 c - b5 pt9a 0 t di pt13a 0 t di a4 pt8b 0 c - pt12b 0 c - b6 pt8a 0 t csn pt12a 0 t csn e6 pt7b 0 c - pt11b 0 c - - gndio0 0 - - gndio0 0 - - d6 pt7a 0 t - pt11a 0 t - d5 pt6b 0 c vref2_0 pt10b 0 c vref2_0 a3 pt6a 0 t dqs pt10a 0 t dqs b3 pt5b 0 - - pt9b 0 - - b2 pt4a 0 - - pt8a 0 - - a2 pt3b 0 c - pt7b 0 c - b1 pt3a 0 t - pt7a 0 t - f5 pt2b 0 c - pt6b 0 c - - gndio0 0 - - gndio0 0 - - c5 pt2a 0 t - pt6a 0 t - c4 cfg0 0 - - cfg0 0 - - b4 cfg1 0 - - cfg1 0 - - c3 done 0 - - done 0 - - a1 gnd - - - gnd - - - a16 gnd - - - gnd - - - f11 gnd - - - gnd - - - f6 gnd - - - gnd - - - g10 gnd - - - gnd - - - g7 gnd - - - gnd - - - g8 gnd - - - gnd - - - g9 gnd - - - gnd - - - h10 gnd - - - gnd - - - h7 gnd - - - gnd - - - h8 gnd - - - gnd - - - h9 gnd - - - gnd - - - j10 gnd - - - gnd - - - j7 gnd - - - gnd - - - j8 gnd - - - gnd - - - j9 gnd - - - gnd - - - lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-25 pinout information lattice semiconductor latticexp family data sheet k10 gnd - - - gnd - - - k7 gnd - - - gnd - - - k8 gnd - - - gnd - - - k9 gnd - - - gnd - - - l11 gnd - - - gnd - - - l6 gnd - - - gnd - - - t1 gnd - - - gnd - - - t16 gnd - - - gnd - - - d13 vcc - - - vcc - - - d4 vcc - - - vcc - - - e12 vcc - - - vcc - - - e5 vcc - - - vcc - - - m12 vcc - - - vcc - - - m5 vcc - - - vcc - - - n13 vcc - - - vcc - - - n4 vcc - - - vcc - - - e13 vccaux - - - vccaux - - - e4 vccaux - - - vccaux - - - m13 vccaux - - - vccaux - - - m4 vccaux - - - vccaux - - - f7 vccio0 0 - - vccio0 0 - - f8 vccio0 0 - - vccio0 0 - - f10 vccio1 1 - - vccio1 1 - - f9 vccio1 1 - - vccio1 1 - - g11 vccio2 2 - - vccio2 2 - - h11 vccio2 2 - - vccio2 2 - - j11 vccio3 3 - - vccio3 3 - - k11 vccio3 3 - - vccio3 3 - - l10 vccio4 4 - - vccio4 4 - - l9 vccio4 4 - - vccio4 4 - - l7 vccio5 5 - - vccio5 5 - - l8 vccio5 5 - - vccio5 5 - - j6 vccio6 6 - - vccio6 6 - - k6 vccio6 6 - - vccio6 6 - - g6 vccio7 7 - - vccio7 7 - - h6 vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp6 & lfxp10 logic signal connections: 256 fpbga (cont.) ball number lfxp6 lfxp10 ball function bank differential dual function ball function bank differential dual function
4-26 pinout information lattice semiconductor latticexp family data sheet LFXP15 & lfxp20 logic signal connections: 256 fpbga ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function c2 programn 7 - - programn 7 - - c1 cclk 7 - - cclk 7 - - - gndio7 7 - - gndio7 7 - - - gndio7 7 - - gndio7 7 - - d2 pl7a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a d3 pl7b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a d1 pl9a 7 - - pl9a 7 - - e2 pl10b 7 - vref1_7 pl10b 7 - vref1_7 e1 pl11a 7 t 3 dqs pl11a 7 t 3 dqs f1 pl11b 7 c 3 - pl11b 7 c 3 - - gndio7 7 - - gndio7 7 - - e3 pl12a 7 t - pl12a 7 t - f4 pl12b 7 c - pl12b 7 c - f3 pl13a 7 t 3 - pl13a 7 t 3 - f2 pl13b 7 c 3 - pl13b 7 c 3 - g1 pl15b 7 - - pl15b 7 - - - gndio7 7 - - gndio7 7 - - g3 pl16a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a g2 pl16b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a h1 pl17a 7 t 3 - pl17a 7 t 3 - h2 pl17b 7 c 3 - pl17b 7 c 3 - g4 pl18a 7 - vref2_7 pl18a 7 - vref2_7 g5 pl19b 7 - - pl19b 7 - - j1 pl20a 7 t 3 dqs pl20a 7 t 3 dqs - gndio7 7 - - gndio7 7 - - j2 pl20b 7 c 3 - pl20b 7 c 3 - h3 pl22a 7 t 3 - pl22a 7 t 3 - j3 pl22b 7 c 3 - pl22b 7 c 3 - h4 vccp0 - - - vccp0 - - - h5 gndp0 - - - gndp0 - - - k1 pl24a 6 t pclkt6_0 pl28a 6 t pclkt6_0 - gndio6 6 - - gndio6 6 - - k2 pl24b 6 c pclkc6_0 pl28b 6 c pclkc6_0 j4 pl26a 6 - - pl30a 6 - - j5 pl27b 6 - vref1_6 pl31b 6 - vref1_6 l1 pl28a 6 t 3 dqs pl32a 6 t 3 dqs l2 pl28b 6 c 3 - pl32b 6 c 3 - - gndio6 6 - - gndio6 6 - - m1 pl29a 6 t llm0_pllt_in_a pl33a 6 t llm0_pllt_in_a m2 pl29b 6 c llm0_pllc_in_a pl33b 6 c llm0_pllc_in_a k3 pl30a 6 t 3 - pl34a 6 t 3 - l3 pl30b 6 c 3 - pl34b 6 c 3 -
4-27 pinout information lattice semiconductor latticexp family data sheet l4 pl32a 6 - - pl36a 6 - - - gndio6 6 - - gndio6 6 - - k4 pl33a 6 t - pl37a 6 t - k5 pl33b 6 c - pl37b 6 c - n1 pl35a 6 - vref2_6 pl39a 6 - vref2_6 n2 pl36b 6 - - pl40b 6 - - p1 pl37a 6 t 3 dqs pl41a 6 t 3 dqs p2 pl37b 6 c 3 - pl41b 6 c 3 - - gndio6 6 - - gndio6 6 - - l5 pl38a 6 t llm0_pllt_fb_a pl42a 6 t llm0_pllt_fb_a m6 pl38b 6 c llm0_pllc_fb_a pl42b 6 c llm0_pllc_fb_a m3 pl39a 6 t 3 - pl43a 6 t 3 - n3 pl39b 6 c 3 - pl43b 6 c 3 - - gndio6 6 - - gndio6 6 - - p4 sleepn 1 /toe 2 - - - sleepn 1 /toe 2 -- - p3 initn 5 - - initn 5 - - - gndio5 5 - - gndio5 5 - - - gndio5 5 - - gndio5 5 - - - gndio5 5 - - gndio5 5 - - r4 pb11a 5 t - pb15a 5 t - n5 pb11b 5 c - pb15b 5 c - p5 pb12a 5 t vref1_5 pb16a 5 t vref1_5 - gndio5 5 - - gndio5 5 - - r1 pb12b 5 c - pb16b 5 c - n6 pb13a 5 - - pb17a 5 - - m7 pb14b 5 - - pb18b 5 - - r2 pb15a 5 t dqs pb19a 5 t dqs t2 pb15b 5 c - pb19b 5 c - r3 pb16a 5 t - pb20a 5 t - t3 pb16b 5 c - pb20b 5 c - t4 pb17a 5 t - pb21a 5 t - r5 pb17b 5 c vref2_5 pb21b 5 c vref2_5 n7 pb18a 5 t - pb22a 5 t - - gndio5 5 - - gndio5 5 - - m8 pb18b 5 c - pb22b 5 c - t5 pb19a 5 t - pb23a 5 t - p6 pb19b 5 c - pb23b 5 c - t6 pb20a 5 t - pb24a 5 t - r6 pb20b 5 c - pb24b 5 c - p7 pb21a 5 - - pb25a 5 - - n8 pb22b 5 - - pb26b 5 - - r7 pb23a 5 t dqs pb27a 5 t dqs LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-28 pinout information lattice semiconductor latticexp family data sheet t7 pb23b 5 c - pb27b 5 c - - gndio5 5 - - gndio5 5 - - p8 pb24a 5 t - pb28a 5 t - t8 pb24b 5 c - pb28b 5 c - r8 pb25a 5 t - pb29a 5 t - t9 pb25b 5 c - pb29b 5 c - r9 pb26a 4 t - pb30a 4 t - p9 pb26b 4 c - pb30b 4 c - t10 pb27a 4 t pclkt4_0 pb31a 4 t pclkt4_0 t11 pb27b 4 c pclkc4_0 pb31b 4 c pclkc4_0 - gndio4 4 - - gndio4 4 - - r10 pb28a 4 t - pb32a 4 t - p10 pb28b 4 c - pb32b 4 c - n9 pb29a 4 - - pb33a 4 - - m9 pb30b 4 - - pb34b 4 - - r12 pb31a 4 t dqs pb35a 4 t dqs t12 pb31b 4 c vref1_4 pb35b 4 c vref1_4 p13 pb32a 4 t - pb36a 4 t - r13 pb32b 4 c - pb36b 4 c - m11 pb33a 4 t - pb37a 4 t - - gndio4 4 - - gndio4 4 - - n11 pb33b 4 c - pb37b 4 c - n10 pb34a 4 t - pb38a 4 t - m10 pb34b 4 c - pb38b 4 c - t13 pb35a 4 t - pb39a 4 t - p14 pb35b 4 c - pb39b 4 c - r11 pb36a 4 t vref2_4 pb40a 4 t vref2_4 p12 pb36b 4 c - pb40b 4 c - t14 pb37a 4 - - pb41a 4 - - r14 pb38b 4 - - pb42b 4 - - - gndio4 4 - - gndio4 4 - - p11 pb39a 4 t dqs pb43a 4 t dqs n12 pb39b 4 c - pb43b 4 c - t15 pb40a 4 t - pb44a 4 t - r15 pb40b 4 c - pb44b 4 c - - gndio4 4 - - gndio4 4 - - - gndio4 4 - - gndio4 4 - - - gndio4 4 - - gndio4 4 - - - gndio3 3 - - gndio3 3 - - - gndio3 3 - - gndio3 3 - - p15 pr38b 3 c rlm0_pllc_fb_a pr42b 3 c rlm0_pllc_fb_a n15 pr38a 3 t rlm0_pllt_fb_a pr42a 3 t rlm0_pllt_fb_a LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-29 pinout information lattice semiconductor latticexp family data sheet p16 pr37b 3 c 3 - pr41b 3 c 3 - r16 pr37a 3 t 3 dqs pr41a 3 t 3 dqs m15 pr36b 3 - - pr40b 3 - - n14 pr35a 3 - vref1_3 pr39a 3 - vref1_3 - gndio3 3 - - gndio3 3 - - m14 pr33b 3 c - pr37b 3 c - l13 pr33a 3 t - pr37a 3 t - l15 pr32b 3 c 3 - pr36b 3 c 3 - l14 pr32a 3 t 3 - pr36a 3 t 3 - l12 pr30a 3 - - pr34a 3 - - m16 pr29b 3 c rlm0_pllc_in_a pr33b 3 c rlm0_pllc_in_a n16 pr29a 3 t rlm0_pllt_in_a pr33a 3 t rlm0_pllt_in_a - gndio3 3 - - gndio3 3 - - k14 pr28b 3 c 3 - pr32b 3 c 3 - k15 pr28a 3 t 3 dqs pr32a 3 t 3 dqs k12 pr27b 3 - - pr31b 3 - - k13 pr26a 3 - vref2_3 pr30a 3 - vref2_3 l16 pr25b 3 c 3 - pr29b 3 c 3 - k16 pr25a 3 t 3 - pr29a 3 t 3 - - gndio3 3 - - gndio3 3 - - j15 pr23b 3 c 3 - pr27b 3 c 3 - j14 pr23a 3 t 3 - pr27a 3 t 3 - j13 gndp1 - - - gndp1 - - - j12 vccp1 - - - vccp1 - - - - gndio2 2 - - gndio2 2 - - j16 pr21b 2 c pclkc2_0 pr21b 2 c pclkc2_0 h16 pr21a 2 t pclkt2_0 pr21a 2 t pclkt2_0 h13 pr20b 2 c 3 - pr20b 2 c 3 - h12 pr20a 2 t 3 dqs pr20a 2 t 3 dqs h15 pr19b 2 - - pr19b 2 - - h14 pr18a 2 - vref1_2 pr18a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - g15 pr17b 2 c 3 - pr17b 2 c 3 - g14 pr17a 2 t 3 - pr17a 2 t 3 - g16 pr16b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a f16 pr16a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a g13 pr15b 2 - - pr15b 2 - - - gndio2 2 - - gndio2 2 - - g12 pr12b 2 c - pr12b 2 c - f13 pr12a 2 t - pr12a 2 t - b16 pr11b 2 c 3 - pr11b 2 c 3 - c16 pr11a 2 t 3 dqs pr11a 2 t 3 dqs LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-30 pinout information lattice semiconductor latticexp family data sheet - gndio2 2 - - gndio2 2 - - f15 pr10b 2 - - pr10b 2 - - e15 pr9a 2 - vref2_2 pr9a 2 - vref2_2 f14 pr8b 2 c 3 - pr8b 2 c 3 - e14 pr8a 2 t 3 - pr8a 2 t 3 - d15 pr7b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a c15 pr7a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a - gndio2 2 - - gndio2 2 - - e16 tdo - - - tdo - - - d16 vccj - - - vccj - - - d14 tdi - - - tdi - - - c14 tms - - - tms - - - b14 tck - - - tck - - - - gndio1 1 - - gndio1 1 - - - gndio1 1 - - gndio1 1 - - - gndio1 1 - - gndio1 1 - - a15 pt40b 1 c - pt44b 1 c - b15 pt40a 1 t - pt44a 1 t - d12 pt39b 1 c vref1_1 pt43b 1 c vref1_1 - gndio1 1 - - gndio1 1 - - c11 pt39a 1 t dqs pt43a 1 t dqs a14 pt38b 1 - - pt42b 1 - - b13 pt37a 1 - - pt41a 1 - - f12 pt36b 1 c - pt40b 1 c - e11 pt36a 1 t - pt40a 1 t - a13 pt35b 1 c - pt39b 1 c - c13 pt35a 1 t d0 pt39a 1 t d0 c10 pt34b 1 c d1 pt38b 1 c d1 e10 pt34a 1 t vref2_1 pt38a 1 t vref2_1 a12 pt33b 1 c - pt37b 1 c - b12 pt33a 1 t d2 pt37a 1 t d2 - gndio1 1 - - gndio1 1 - - c12 pt32b 1 c d3 pt36b 1 c d3 a11 pt32a 1 t - pt36a 1 t - b11 pt31b 1 c - pt35b 1 c - d11 pt31a 1 t dqs pt35a 1 t dqs b9 pt30b 1 - - pt34b 1 - - d9 pt29a 1 - d4 pt33a 1 - d4 a10 pt28b 1 c - pt32b 1 c - b10 pt28a 1 t d5 pt32a 1 t d5 - gndio1 1 - - gndio1 1 - - d10 pt27b 1 c d6 pt31b 1 c d6 LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-31 pinout information lattice semiconductor latticexp family data sheet a9 pt27a 1 t - pt31a 1 t - c9 pt26b 1 c d7 pt30b 1 c d7 c8 pt26a 1 t - pt30a 1 t - e9 pt25b 0 c busy pt29b 0 c busy - gndio0 0 - - gndio0 0 - - b8 pt25a 0 t cs1n pt29a 0 t cs1n a8 pt24b 0 c pclkc0_0 pt28b 0 c pclkc0_0 a7 pt24a 0 t pclkt0_0 pt28a 0 t pclkt0_0 b7 pt23b 0 c - pt27b 0 c - c7 pt23a 0 t dqs pt27a 0 t dqs e8 pt22b 0 - - pt26b 0 - - d8 pt21a 0 - dout pt25a 0 - dout a6 pt20b 0 c - pt24b 0 c - - gndio0 0 - - gndio0 0 - - c6 pt20a 0 t writen pt24a 0 t writen e7 pt19b 0 c - pt23b 0 c - d7 pt19a 0 t vref1_0 pt23a 0 t vref1_0 a5 pt18b 0 c - pt22b 0 c - b5 pt18a 0 t di pt22a 0 t di a4 pt17b 0 c - pt21b 0 c - b6 pt17a 0 t csn pt21a 0 t csn e6 pt16b 0 c - pt20b 0 c - d6 pt16a 0 t - pt20a 0 t - d5 pt15b 0 c vref2_0 pt19b 0 c vref2_0 a3 pt15a 0 t dqs pt19a 0 t dqs b3 pt14b 0 - - pt18b 0 - - b2 pt13a 0 - - pt17a 0 - - - gndio0 0 - - gndio0 0 - - a2 pt12b 0 c - pt16b 0 c - b1 pt12a 0 t - pt16a 0 t - f5 pt11b 0 c - pt15b 0 c - c5 pt11a 0 t - pt15a 0 t - - gndio0 0 - - gndio0 0 - - - gndio0 0 - - gndio0 0 - - - gndio0 0 - - gndio0 0 - - c4 cfg0 0 - - cfg0 0 - - b4 cfg1 0 - - cfg1 0 - - c3 done 0 - - done 0 - - a1 gnd - - - gnd - - - a16 gnd - - - gnd - - - f11 gnd - - - gnd - - - f6 gnd - - - gnd - - - LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-32 pinout information lattice semiconductor latticexp family data sheet g10 gnd - - - gnd - - - g7 gnd - - - gnd - - - g8 gnd - - - gnd - - - g9 gnd - - - gnd - - - h10 gnd - - - gnd - - - h7 gnd - - - gnd - - - h8 gnd - - - gnd - - - h9 gnd - - - gnd - - - j10 gnd - - - gnd - - - j7 gnd - - - gnd - - - j8 gnd - - - gnd - - - j9 gnd - - - gnd - - - k10 gnd - - - gnd - - - k7 gnd - - - gnd - - - k8 gnd - - - gnd - - - k9 gnd - - - gnd - - - l11 gnd - - - gnd - - - l6 gnd - - - gnd - - - t1 gnd - - - gnd - - - t16 gnd - - - gnd - - - d13 vcc - - - vcc - - - d4 vcc - - - vcc - - - e12 vcc - - - vcc - - - e5 vcc - - - vcc - - - m12 vcc - - - vcc - - - m5 vcc - - - vcc - - - n13 vcc - - - vcc - - - n4 vcc - - - vcc - - - e13 vccaux - - - vccaux - - - e4 vccaux - - - vccaux - - - m13 vccaux - - - vccaux - - - m4 vccaux - - - vccaux - - - f7 vccio0 0 - - vccio0 0 - - f8 vccio0 0 - - vccio0 0 - - f10 vccio1 1 - - vccio1 1 - - f9 vccio1 1 - - vccio1 1 - - g11 vccio2 2 - - vccio2 2 - - h11 vccio2 2 - - vccio2 2 - - j11 vccio3 3 - - vccio3 3 - - k11 vccio3 3 - - vccio3 3 - - l10 vccio4 4 - - vccio4 4 - - l9 vccio4 4 - - vccio4 4 - - LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-33 pinout information lattice semiconductor latticexp family data sheet l7 vccio5 5 - - vccio5 5 - - l8 vccio5 5 - - vccio5 5 - - j6 vccio6 6 - - vccio6 6 - - k6 vccio6 6 - - vccio6 6 - - g6 vccio7 7 - - vccio7 7 - - h6 vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. LFXP15 & lfxp20 logic signal connections: 256 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-34 pinout information lattice semiconductor latticexp family data sheet lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function f4 programn 7 - - programn 7 - - programn 7 - - g4 cclk 7 - - cclk 7 - - cclk 7 - - - gndio7 7 - - gndio7 7 - - gndio7 7 - - d2 pl2a 7 t 3 - pl6a 7 t 3 - pl6a 7 t 3 - d1 pl2b 7 c 3 - pl6b 7 c 3 - pl6b 7 c 3 - - gndio7 7 - - gndio7 7 - - gndio7 7 - - e2 pl3a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a e3 pl3b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a f3 pl4a 7 t 3 - pl8a 7 t 3 - pl8a 7 t 3 - f2 pl4b 7 c 3 - pl8b 7 c 3 - pl8b 7 c 3 - h4 pl5a 7 - - pl9a 7 - - pl9a 7 - - h3 pl6b 7 - vref1_7 pl10b 7 - vref1_7 pl10b 7 - vref1_7 g3 pl7a 7 t 3 dqs pl11a 7 t 3 dqs pl11a 7 t 3 dqs g2 pl7b 7 c 3 - pl11b 7 c 3 - pl11b 7 c 3 - - gndio7 7 - - gndio7 7 - - gndio7 7 - - f1 pl8a 7 t - pl12a 7 t - pl12a 7 t - e1 pl8b 7 c - pl12b 7 c - pl12b 7 c - j4 pl9a 7 t 3 - pl13a 7 t 3 - pl13a 7 t 3 - k4 pl9b 7 c 3 - pl13b 7 c 3 - pl13b 7 c 3 - g1 pl11a 7 t 3 - pl15a 7 t 3 - pl15a 7 t 3 - h2 pl11b 7 c 3 - pl15b 7 c 3 - pl15b 7 c 3 - - gndio7 7 - - gndio7 7 - - gndio7 7 - - j2 pl12a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a h1 pl12b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a j1 pl13a 7 t 3 - pl17a 7 t 3 - pl17a 7 t 3 - k2 pl13b 7 c 3 - pl17b 7 c 3 - pl17b 7 c 3 - k3 pl14a 7 - vref2_7 pl18a 7 - vref2_7 pl18a 7 - vref2_7 j3 pl15b 7 - - pl19b 7 - - pl19b 7 - - k1 pl16a 7 t 3 dqs pl20a 7 t 3 dqs pl20a 7 t 3 dqs - gndio7 7 - - gndio7 7 - - gndio7 7 - - l2 pl16b 7 c 3 - pl20b 7 c 3 - pl20b 7 c 3 - l3 pl17a 7 t - pl21a 7 t - pl21a 7 t - l4 pl17b 7 c - pl21b 7 c - pl21b 7 c - l1 pl18a 7 t 3 - pl22a 7 t 3 - pl22a 7 t 3 - m1 pl18b 7 c 3 - pl22b 7 c 3 - pl22b 7 c 3 - m2 vccp0 - - - vccp0 - - - vccp0 - - - n1 gndp0 - - - gndp0 - - - gndp0 - - - m3 pl19a 6 t 3 - pl23a 6 t 3 - pl27a 6 t 3 - m4 pl19b 6 c 3 - pl23b 6 c 3 - pl27b 6 c 3 - p1 pl20a 6 t pclkt6_0 pl24a 6 t pclkt6_0 pl28a 6 t pclkt6_0 - gndio6 6 - - gndio6 6 - - gndio6 6 - - n2 pl20b 6 c pclkc6_0 pl24b 6 c pclkc6_0 pl28b 6 c pclkc6_0 r1 pl21a 6 t 3 - pl25a 6 t 3 - pl29a 6 t 3 - p2 pl21b 6 c 3 - pl25b 6 c 3 - pl29b 6 c 3 - n3 pl22a 6 - - pl26a 6 - - pl30a 6 - - n4 pl23b 6 - vref1_6 pl27b 6 - vref1_6 pl31b 6 - vref1_6 t1 pl24a 6 t 3 dqs pl28a 6 t 3 dqs pl32a 6 t 3 dqs r2 pl24b 6 c 3 - pl28b 6 c 3 - pl32b 6 c 3 - - gndio6 6 - - gndio6 6 - - gndio6 6 - -
4-35 pinout information lattice semiconductor latticexp family data sheet u1 pl25a 6 t llm0_pllt_in_a pl29a 6 t llm0_pllt_in_a pl33a 6 t llm0_pllt_in_a t2 pl25b 6 c llm0_pllc_in_a pl29b 6 c llm0_pllc_in_a pl33b 6 c llm0_pllc_in_a v1 pl26a 6 t 3 - pl30a 6 t 3 - pl34a 6 t 3 - u2 pl26b 6 c 3 - pl30b 6 c 3 - pl34b 6 c 3 - w1 pl28a 6 t 3 - pl32a 6 t 3 - pl36a 6 t 3 - v2 pl28b 6 c 3 - pl32b 6 c 3 - pl36b 6 c 3 - - gndio6 6 - - gndio6 - - - gndio6 6 - - p3 pl29a 6 t - pl33a 6 t - pl37a 6 t - p4 pl29b 6 c - pl33b 6 c - pl37b 6 c - y1 pl30a 6 t 3 - pl34a 6 t 3 - pl38a 6 t 3 - w2 pl30b 6 c 3 - pl34b 6 c 3 - pl38b 6 c 3 - r3 pl31a 6 - vref2_6 pl35a 6 - vref2_6 pl39a 6 - vref2_6 r4 pl32b 6 - - pl36b 6 - - pl40b 6 - - t3 pl33a 6 t 3 dqs pl37a 6 t 3 dqs pl41a 6 t 3 dqs t4 pl33b 6 c 3 - pl37b 6 c 3 - pl41b 6 c 3 - - gndio6 6 - - gndio6 6 - - gndio6 6 - - v4 pl34a 6 t llm0_pllt_fb_a pl38a 6 t llm0_pllt_fb_a pl42a 6 t llm0_pllt_fb_a v3 pl34b 6 c llm0_pllc_fb_a pl38b 6 c llm0_pllc_fb_a pl42b 6 c llm0_pllc_fb_a u4 pl35a 6 t 3 - pl39a 6 t 3 - pl43a 6 t 3 - u3 pl35b 6 c 3 - pl39b 6 c 3 - pl43b 6 c 3 - - gndio6 6 - - gndio6 6 - - gndio6 6 - - w5 sleepn 1 / toe 2 -- - sleepn 1 / toe 2 -- - sleepn 1 / toe 2 -- - y2 initn 5 - - initn 5 - - initn 5 - - - gndio5 5 - - gndio5 5 - - gndio5 5 - - - gndio5 5 - - gndio5 5 - - gndio5 5 - - y3 - - - - pb3b 5 - - pb7b 5 - - w3 - - - - pb4a 5 t - pb8a 5 t - w4 - - - - pb4b 5 c - pb8b 5 c - aa2 - - - - pb5a 5 - - pb9a 5 - - aa1 - - - - pb6b 5 - - pb10b 5 - - w6 pb2a 5 - - pb7a 5 t dqs pb11a 5 t dqs w7 - - - - pb7b 5 c - pb11b 5 c - y4 pb3a 5 t - pb8a 5 t - pb12a 5 t - - gndio5 5 - - gndio5 5 - - gndio5 5 - - y5 pb3b 5 c - pb8b 5 c - pb12b 5 c - ab2 pb4a 5 t - pb9a 5 t - pb13a 5 t - aa3 pb4b 5 c - pb9b 5 c - pb13b 5 c - ab3 pb5a 5 t - pb10a 5 t - pb14a 5 t - aa4 pb5b 5 c - pb10b 5 c - pb14b 5 c - w8 pb6a 5 t - pb11a 5 t - pb15a 5 t - w9 pb6b 5 c - pb11b 5 c - pb15b 5 c - ab4 pb7a 5 t vref1_5 pb12a 5 t vref1_5 pb16a 5 t vref1_5 - gndio5 5 - - gndio5 5 - - gndio5 5 - - aa5 pb7b 5 c - pb12b 5 c - pb16b 5 c - ab5 pb8a 5 - - pb13a 5 - - pb17a 5 - - y6 pb9b 5 - - pb14b 5 - - pb18b 5 - - aa6 pb10a 5 t dqs pb15a 5 t dqs pb19a 5 t dqs ab6 pb10b 5 c - pb15b 5 c - pb19b 5 c - y9 pb11a 5 t - pb16a 5 t - pb20a 5 t - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-36 pinout information lattice semiconductor latticexp family data sheet y10 pb11b 5 c - pb16b 5 c - pb20b 5 c - aa7 pb12a 5 t - pb17a 5 t - pb21a 5 t - ab7 pb12b 5 c vref2_5 pb17b 5 c vref2_5 pb21b 5 c vref2_5 y7 pb13a 5 t - pb18a 5 t - pb22a 5 t - - gndio5 5 - - gndio5 5 - - gndio5 5 - - aa8 pb13b 5 c - pb18b 5 c - pb22b 5 c - ab8 pb14a 5 t - pb19a 5 t - pb23a 5 t - y8 pb14b 5 c - pb19b 5 c - pb23b 5 c - ab9 pb15a 5 t - pb20a 5 t - pb24a 5 t - aa9 pb15b 5 c - pb20b 5 c - pb24b 5 c - w10 pb16a 5 - - pb21a 5 - - pb25a 5 - - w11 pb17b 5 - - pb22b 5 - - pb26b 5 - - ab10 pb18a 5 t dqs pb23a 5 t dqs pb27a 5 t dqs aa10 pb18b 5 c - pb23b 5 c - pb27b 5 c - - gndio5 5 - - gndio5 5 - - gndio5 5 - - aa11 pb19a 5 t - pb24a 5 t - pb28a 5 t - ab11 pb19b 5 c - pb24b 5 c - pb28b 5 c - y11 pb20a 5 t - pb25a 5 t - pb29a 5 t - y12 pb20b 5 c - pb25b 5 c - pb29b 5 c - ab12 pb21a 4 t - pb26a 4 t - pb30a 4 t - aa12 pb21b 4 c - pb26b 4 c - pb30b 4 c - ab13 pb22a 4 t pclkt4_0 pb27a 4 t pclkt4_0 pb31a 4 t pclkt4_0 aa13 pb22b 4 c pclkc4_0 pb27b 4 c pclkc4_0 pb31b 4 c pclkc4_0 - gndio4 4 - - gndio4 4 - - gndio4 4 - - aa14 pb23a 4 t - pb28a 4 t - pb32a 4 t - ab14 pb23b 4 c - pb28b 4 c - pb32b 4 c - w12 pb24a 4 - - pb29a 4 - - pb33a 4 - - w13 pb25b 4 - - pb30b 4 - - pb34b 4 - - aa15 pb26a 4 t dqs pb31a 4 t dqs pb35a 4 t dqs ab15 pb26b 4 c vref1_4 pb31b 4 c vref1_4 pb35b 4 c vref1_4 aa16 pb27a 4 t - pb32a 4 t - pb36a 4 t - ab16 pb27b 4 c - pb32b 4 c - pb36b 4 c - y17 pb28a 4 t - pb33a 4 t - pb37a 4 t - - gndio4 4 - - gndio4 4 - - gndio4 4 - - aa17 pb28b 4 c - pb33b 4 c - pb37b 4 c - y13 pb29a 4 t - pb34a 4 t - pb38a 4 t - y14 pb29b 4 c - pb34b 4 c - pb38b 4 c - ab17 pb30a 4 t - pb35a 4 t - pb39a 4 t - y18 pb30b 4 c - pb35b 4 c - pb39b 4 c - aa18 pb31a 4 t vref2_4 pb36a 4 t vref2_4 pb40a 4 t vref2_4 ab18 pb31b 4 c - pb36b 4 c - pb40b 4 c - y19 pb32a 4 - - pb37a 4 - - pb41a 4 - - ab19 pb33b 4 - - pb38b 4 - - pb42b 4 - - - gndio4 4 - - gndio4 4 - - gndio4 4 - - aa19 pb34a 4 t dqs pb39a 4 t dqs pb43a 4 t dqs y20 pb34b 4 c - pb39b 4 c - pb43b 4 c - w14 pb35a 4 t - pb40a 4 t - pb44a 4 t - w15 pb35b 4 c - pb40b 4 c - pb44b 4 c - ab20 pb36a 4 t - pb41a 4 t - pb45a 4 t - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-37 pinout information lattice semiconductor latticexp family data sheet aa20 pb36b 4 c - pb41b 4 c - pb45b 4 c - ab21 pb37a 4 t - pb42a 4 t - pb46a 4 t - aa21 pb37b 4 c - pb42b 4 c - pb46b 4 c - aa22 pb38a 4 t - pb43a 4 t - pb47a 4 t - y21 pb38b 4 c - pb43b 4 c - pb47b 4 c - - gndio4 4 - - gndio4 4 - - gndio4 4 - - w16 pb39a 4 - - pb44a 4 t - pb48a 4 t - w17 - - - - pb44b 4 c - pb48b 4 c - y15 - - - - pb45a 4 - - pb49a 4 - - y16 - - - - pb46b 4 - - pb50b 4 - - w19 - - - - pb47a 4 t dqs pb51a 4 t dqs w18 - - - - pb47b 4 c - pb51b 4 c - w20 - - - - pb48a 4 - - pb52a 4 - - - gndio4 4 - - gndio4 4 - - gndio4 4 - - - gndio4 4 - - gndio4 4 - - gndio4 4 - - - gndio3 3 - - gndio3 3 - - gndio3 3 - - t20 pr35b 3 c 3 - pr39b 3 c 3 - pr43b 3 c 3 - t19 pr35a 3 t 3 - pr39a 3 t 3 - pr43a 3 t 3 - - gndio3 3 - - gndio3 3 - - gndio3 3 - - u19 pr34b 3 c rlm0_pllc_fb_a pr38b 3 c rlm0_pllc_fb_a pr42b 3 c rlm0_pllc_fb_a u20 pr34a 3 t rlm0_pllt_fb_a pr38a 3 t rlm0_pllt_fb_a pr42a 3 t rlm0_pllt_fb_a v19 pr33b 3 c 3 - pr37b 3 c 3 - pr41b 3 c 3 - v20 pr33a 3 t 3 dqs pr37a 3 t 3 dqs pr41a 3 t 3 dqs r19 pr32b 3 - - pr36b 3 - - pr40b 3 - - r20 pr31a 3 - vref1_3 pr35a 3 - vref1_3 pr39a 3 - vref1_3 w21 pr30b 3 c 3 - pr34b 3 c 3 - pr38b 3 c 3 - y22 pr30a 3 t 3 - pr34a 3 t 3 - pr38a 3 t 3 - - gndio3 3 - - gndio3 3 - - gndio3 3 - - p19 pr29b 3 c - pr33b 3 c - pr37b 3 c - p20 pr29a 3 t - pr33a 3 t - pr37a 3 t - v21 pr28b 3 c 3 - pr32b 3 c 3 - pr36b 3 c 3 - w22 pr28a 3 t 3 - pr32a 3 t 3 - pr36a 3 t 3 - u21 pr26b 3 c 3 - pr30b 3 c 3 - pr34b 3 c 3 - v22 pr26a 3 t 3 - pr30a 3 t 3 - pr34a 3 t 3 - t21 pr25b 3 c rlm0_pllc_in_a pr29b 3 c rlm0_pllc_in_a pr33b 3 c rlm0_pllc_in_a u22 pr25a 3 t rlm0_pllt_in_a pr29a 3 t rlm0_pllt_in_a pr33a 3 t rlm0_pllt_in_a - gndio3 3 - - gndio3 3 - - gndio3 3 - - r21 pr24b 3 c 3 - pr28b 3 c 3 - pr32b 3 c 3 - t22 pr24a 3 t 3 dqs pr28a 3 t 3 dqs pr32a 3 t 3 dqs n19 pr23b 3 - - pr27b 3 - - pr31b 3 - - n20 pr22a 3 - vref2_3 pr26a 3 - vref2_3 pr30a 3 - vref2_3 r22 pr21b 3 c 3 - pr25b 3 c 3 - pr29b 3 c 3 - p22 pr21a 3 t 3 - pr25a 3 t 3 - pr29a 3 t 3 - p21 pr20b 3 c - pr24b 3 c - pr28b 3 c - n21 pr20a 3 t - pr24a 3 t - pr28a 3 t - - gndio3 3 - - gndio3 3 - - gndio3 3 - - m20 pr19b 3 c 3 - pr23b 3 c 3 - pr27b 3 c 3 - m19 pr19a 3 t 3 - pr23a 3 t 3 - pr27a 3 t 3 - n22 gndp1 - - - gndp1 - - - gndp1 - - - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-38 pinout information lattice semiconductor latticexp family data sheet m21 vccp1 - - - vccp1 - - - vccp1 - - - - gndio2 2 - - gndio2 2 - - gndio2 2 - - m22 pr18b 2 c 3 - pr22b 2 c 3 - pr22b 2 c 3 - l22 pr18a 2 t 3 - pr22a 2 t 3 - pr22a 2 t 3 - k22 pr17b 2 c pclkc2_0 pr21b 2 c pclkc2_0 pr21b 2 c pclkc2_0 k21 pr17a 2 t pclkt2_0 pr21a 2 t pclkt2_0 pr21a 2 t pclkt2_0 l19 pr16b 2 c 3 - pr20b 2 c 3 - pr20b 2 c 3 - k20 pr16a 2 t 3 dqs pr20a 2 t 3 dqs pr20a 2 t 3 dqs l20 pr15b 2 - - pr19b 2 - - pr19b 2 - - l21 pr14a 2 - vref1_2 pr18a 2 - vref1_2 pr18a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - gndio2 2 - - j22 pr13b 2 c 3 - pr17b 2 c 3 - pr17b 2 c 3 - j21 pr13a 2 t 3 - pr17a 2 t 3 - pr17a 2 t 3 - h22 pr12b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a h21 pr12a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a k19 pr11b 2 c 3 - pr15b 2 c 3 - pr15b 2 c 3 - j19 pr11a 2 t 3 - pr15a 2 t 3 - pr15a 2 t 3 - - gndio2 2 - - gndio2 2 - - gndio2 2 - - j20 pr9b 2 c 3 - pr13b 2 c 3 - pr13b 2 c 3 - h20 pr9a 2 t 3 - pr13a 2 t 3 - pr13a 2 t 3 - h19 pr8b 2 c - pr12b 2 c - pr12b 2 c - g19 pr8a 2 t - pr12a 2 t - pr12a 2 t - g22 pr7b 2 c 3 - pr11b 2 c 3 - pr11b 2 c 3 - g21 pr7a 2 t 3 dqs pr11a 2 t 3 dqs pr11a 2 t 3 dqs - gndio2 2 - - gndio2 2 - - gndio2 2 - - f20 pr6b 2 - - pr10b 2 - - pr10b 2 - - g20 pr5a 2 - vref2_2 pr9a 2 - vref2_2 pr9a 2 - vref2_2 f22 pr4b 2 c 3 - pr8b 2 c 3 - pr8b 2 c 3 - f21 pr4a 2 t 3 - pr8a 2 t 3 - pr8a 2 t 3 - e22 pr3b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a e21 pr3a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a d22 pr2b 2 c 3 - pr6b 2 c 3 - pr6b 2 c 3 - d21 pr2a 2 t 3 - pr6a 2 t 3 - pr6a 2 t 3 - - gndio2 2 - - gndio2 2 - - gndio2 2 - - f19 tdo - - - tdo - - - tdo - -- e20 vccj - - - vccj - - - vccj - -- d20 tdi - - - tdi - - - tdi - -- d19 tms - - - tms - - - tms - -- d18 tck - - - tck - - - tck - -- - gndio1 1 - - gndio1 1 - - gndio1 1 - - e19 - - - - pt48a 1 - - pt52a 1 - - d17 - - - - pt47b 1 c - pt51b 1 c - d16 - - - - pt47a 1 t dqs pt51a 1 t dqs c16 - - - - pt46b 1 - - pt50b 1 - - c15 - - - - pt45a 1 - - pt49a 1 - - c17 - - - - pt44b 1 c - pt48b 1 c - c18 pt39a 1 - - pt44a 1 t - pt48a 1 t - c19 pt38b 1 c - pt43b 1 c - pt47b 1 c - - gndio1 1 - - gndio1 1 - - gndio1 1 - - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-39 pinout information lattice semiconductor latticexp family data sheet c20 pt38a 1 t - pt43a 1 t - pt47a 1 t - c21 pt37b 1 c - pt42b 1 c - pt46b 1 c - c22 pt37a 1 t - pt42a 1 t - pt46a 1 t - b22 pt36b 1 c - pt41b 1 c - pt45b 1 c - a21 pt36a 1 t - pt41a 1 t - pt45a 1 t - d15 pt35b 1 c - pt40b 1 c - pt44b 1 c - d14 pt35a 1 t - pt40a 1 t - pt44a 1 t - b21 pt34b 1 c vref1_1 pt39b 1 c vref1_1 pt43b 1 c vref1_1 - gndio1 1 - - gndio1 1 - - gndio1 1 - - a20 pt34a 1 t dqs pt39a 1 t dqs pt43a 1 t dqs b20 pt33b 1 - - pt38b 1 - - pt42b 1 - - a19 pt32a 1 - - pt37a 1 - - pt41a 1 - - b19 pt31b 1 c - pt36b 1 c - pt40b 1 c - a18 pt31a 1 t - pt36a 1 t - pt40a 1 t - c14 pt30b 1 c - pt35b 1 c - pt39b 1 c - c13 pt30a 1 t d0 pt35a 1 t d0 pt39a 1 t d0 b18 pt29b 1 c d1 pt34b 1 c d1 pt38b 1 c d1 a17 pt29a 1 t vref2_1 pt34a 1 t vref2_1 pt38a 1 t vref2_1 b17 pt28b 1 c - pt33b 1 c - pt37b 1 c - a16 pt28a 1 t d2 pt33a 1 t d2 pt37a 1 t d2 - gndio1 1 - - gndio1 1 - - gndio1 1 - - b16 pt27b 1 c d3 pt32b 1 c d3 pt36b 1 c d3 a15 pt27a 1 t - pt32a 1 t - pt36a 1 t - b15 pt26b 1 c - pt31b 1 c - pt35b 1 c - a14 pt26a 1 t dqs pt31a 1 t dqs pt35a 1 t dqs d13 pt25b 1 - - pt30b 1 - - pt34b 1 - - d12 pt24a 1 - d4 pt29a 1 - d4 pt33a 1 - d4 b14 pt23b 1 c - pt28b 1 c - pt32b 1 c - a13 pt23a 1 t d5 pt28a 1 t d5 pt32a 1 t d5 - gndio1 1 - - gndio1 1 - - gndio1 1 - - b13 pt22b 1 c d6 pt27b 1 c d6 pt31b 1 c d6 a12 pt22a 1 t - pt27a 1 t - pt31a 1 t - b12 pt21b 1 c d7 pt26b 1 c d7 pt30b 1 c d7 c12 pt21a 1 t - pt26a 1 t - pt30a 1 t - c11 pt20b 0 c busy pt25b 0 c busy pt29b 0 c busy - gndio0 0 - - gndio0 0 - - gndio0 0 - - b11 pt20a 0 t cs1n pt25a 0 t cs1n pt29a 0 t cs1n a11 pt19b 0 c pclkc0_0 pt24b 0 c pclkc0_0 pt28b 0 c pclkc0_0 a10 pt19a 0 t pclkt0_0 pt24a 0 t pclkt0_0 pt28a 0 t pclkt0_0 b10 pt18b 0 c - pt23b 0 c - pt27b 0 c - b9 pt18a 0 t dqs pt23a 0 t dqs pt27a 0 t dqs d11 pt17b 0 - - pt22b 0 - - pt26b 0 - - d10 pt16a 0 - dout pt21a 0 - dout pt25a 0 - dout a9 pt15b 0 c - pt20b 0 c - pt24b 0 c - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c8 pt15a 0 t writen pt20a 0 t writen pt24a 0 t writen b8 pt14b 0 c - pt19b 0 c - pt23b 0 c - a8 pt14a 0 t vref1_0 pt19a 0 t vref1_0 pt23a 0 t vref1_0 c7 pt13b 0 c - pt18b 0 c - pt22b 0 c - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-40 pinout information lattice semiconductor latticexp family data sheet a7 pt13a 0 t di pt18a 0 t di pt22a 0 t di b7 pt12b 0 c - pt17b 0 c - pt21b 0 c - c6 pt12a 0 t csn pt17a 0 t csn pt21a 0 t csn c10 pt11b 0 c - pt16b 0 c - pt20b 0 c - c9 pt11a 0 t - pt16a 0 t - pt20a 0 t - a6 pt10b 0 c vref2_0 pt15b 0 c vref2_0 pt19b 0 c vref2_0 b6 pt10a 0 t dqs pt15a 0 t dqs pt19a 0 t dqs a5 pt9b 0 - - pt14b 0 - - pt18b 0 - - b5 pt8a 0 - - pt13a 0 - - pt17a 0 - - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c5 pt7b 0 c - pt12b 0 c - pt16b 0 c - a4 pt7a 0 t - pt12a 0 t - pt16a 0 t - d9 pt6b 0 c - pt11b 0 c - pt15b 0 c - d8 pt6a 0 t - pt11a 0 t - pt15a 0 t - b4 pt5b 0 c - pt10b 0 c - pt14b 0 c - a2 pt5a 0 t - pt10a 0 t - pt14a 0 t - a3 pt4b 0 c - pt9b 0 c - pt13b 0 c - b3 pt4a 0 t - pt9a 0 t - pt13a 0 t - c4 pt3b 0 c - pt8b 0 c - pt12b 0 c - c3 pt3a 0 t - pt8a 0 t - pt12a 0 t - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c2 - - - - pt7b 0 c - pt11b 0 c - d3 pt2a 0 - - pt7a 0 t dqs pt11a 0 t dqs d7 - - - - pt6b 0 - - pt10b 0 - - d6 - - - - pt5a 0 - - pt9a 0 - - e4 - - - - pt4b 0 c - pt8b 0 c - d4 - - - - pt4a 0 t - pt8a 0 t - d5 - - - - pt3b 0 - - pt7b 0 - - - gndio0 0 - - gndio0 0 - - gndio0 0 - - - gndio0 0 - - gndio0 0 - - gndio0 0 - - c1 cfg0 0 - - cfg0 0 - - cfg0 0 - - b2 cfg1 0 - - cfg1 0 - - cfg1 0 - - b1 done 0 - - done 0 - - done 0 - - a1 gnd - - - gnd - - - gnd - - - a22 gnd - - - gnd - - - gnd - - - ab1 gnd - - - gnd - - - gnd - - - ab22 gnd - - - gnd - - - gnd - - - h10 gnd - - - gnd - - - gnd - - - h11 gnd - - - gnd - - - gnd - - - h12 gnd - - - gnd - - - gnd - - - h13 gnd - - - gnd - - - gnd - - - h14 gnd - - - gnd - - - gnd - - - j10 gnd - - - gnd - - - gnd - - - j11 gnd - - - gnd - - - gnd - - - j12 gnd - - - gnd - - - gnd - - - j13 gnd - - - gnd - - - gnd - - - j14 gnd - - - gnd - - - gnd - - - j9 gnd - - - gnd - - - gnd - - - k10 gnd - - - gnd - - - gnd - - - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-41 pinout information lattice semiconductor latticexp family data sheet k11 gnd - - - gnd - - - gnd - - - k12 gnd - - - gnd - - - gnd - - - k13 gnd - - - gnd - - - gnd - - - k14 gnd - - - gnd - - - gnd - - - k9 gnd - - - gnd - - - gnd - - - l10 gnd - - - gnd - - - gnd - - - l11 gnd - - - gnd - - - gnd - - - l12 gnd - - - gnd - - - gnd - - - l13 gnd - - - gnd - - - gnd - - - l14 gnd - - - gnd - - - gnd - - - l9 gnd - - - gnd - - - gnd - - - m10 gnd - - - gnd - - - gnd - - - m11 gnd - - - gnd - - - gnd - - - m12 gnd - - - gnd - - - gnd - - - m13 gnd - - - gnd - - - gnd - - - m14 gnd - - - gnd - - - gnd - - - m9 gnd - - - gnd - - - gnd - - - n10 gnd - - - gnd - - - gnd - - - n11 gnd - - - gnd - - - gnd - - - n12 gnd - - - gnd - - - gnd - - - n13 gnd - - - gnd - - - gnd - - - n14 gnd - - - gnd - - - gnd - - - n9 gnd - - - gnd - - - gnd - - - p10 gnd - - - gnd - - - gnd - - - p11 gnd - - - gnd - - - gnd - - - p12 gnd - - - gnd - - - gnd - - - p13 gnd - - - gnd - - - gnd - - - p14 gnd - - - gnd - - - gnd - - - p9 gnd - - - gnd - - - gnd - - - r10 gnd - - - gnd - - - gnd - - - r11 gnd - - - gnd - - - gnd - - - r12 gnd - - - gnd - - - gnd - - - r13 gnd - - - gnd - - - gnd - - - r14 gnd - - - gnd - - - gnd - - - h9 vcc - - - vcc - - - vcc - - - j15 vcc - - - vcc - - - vcc - - - j8 vcc - - - vcc - - - vcc - - - k15 vcc - - - vcc - - - vcc - - - k8 vcc - - - vcc - - - vcc - - - l15 vcc - - - vcc - - - vcc - - - l8 vcc - - - vcc - - - vcc - - - m15 vcc - - - vcc - - - vcc - - - m8 vcc - - - vcc - - - vcc - - - n15 vcc - - - vcc - - - vcc - - - n8 vcc - - - vcc - - - vcc - - - p15 vcc - - - vcc - - - vcc - - - p8 vcc - - - vcc - - - vcc - - - r9 vcc - - - vcc - - - vcc - - - g16 vccaux - - - vccaux - - - vccaux - - - lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-42 pinout information lattice semiconductor latticexp family data sheet g7 vccaux - - - vccaux - - - vccaux - - - t16 vccaux - - - vccaux - - - vccaux - - - t7 vccaux - - - vccaux - - - vccaux - - - g10 vccio0 0 - - vccio0 0 - - vccio0 0 - - g11 vccio0 0 - - vccio0 0 - - vccio0 0 - - g8 vccio0 0 - - vccio0 0 - - vccio0 0 - - g9 vccio0 0 - - vccio0 0 - - vccio0 0 - - h8 vccio0 0 - - vccio0 0 - - vccio0 0 - - g12 vccio1 1 - - vccio1 1 - - vccio1 1 - - g13 vccio1 1 - - vccio1 1 - - vccio1 1 - - g14 vccio1 1 - - vccio1 1 - - vccio1 1 - - g15 vccio1 1 - - vccio1 1 - - vccio1 1 - - h15 vccio1 1 - - vccio1 1 - - vccio1 1 - - h16 vccio2 2 - - vccio2 2 - - vccio2 2 - - j16 vccio2 2 - - vccio2 2 - - vccio2 2 - - k16 vccio2 2 - - vccio2 2 - - vccio2 2 - - l16 vccio2 2 - - vccio2 2 - - vccio2 2 - - m16 vccio3 3 - - vccio3 3 - - vccio3 3 - - n16 vccio3 3 - - vccio3 3 - - vccio3 3 - - p16 vccio3 3 - - vccio3 3 - - vccio3 3 - - r16 vccio3 3 - - vccio3 3 - - vccio3 3 - - r15 vccio4 4 - - vccio4 4 - - vccio4 4 - - t12 vccio4 4 - - vccio4 4 - - vccio4 4 - - t13 vccio4 4 - - vccio4 4 - - vccio4 4 - - t14 vccio4 4 - - vccio4 4 - - vccio4 4 - - t15 vccio4 4 - - vccio4 4 - - vccio4 4 - - r8 vccio5 5 - - vccio5 5 - - vccio5 5 - - t10 vccio5 5 - - vccio5 5 - - vccio5 5 - - t11 vccio5 5 - - vccio5 5 - - vccio5 5 - - t8 vccio5 5 - - vccio5 5 - - vccio5 5 - - t9 vccio5 5 - - vccio5 5 - - vccio5 5 - - m7 vccio6 6 - - vccio6 6 - - vccio6 6 - - n7 vccio6 6 - - vccio6 6 - - vccio6 6 - - p7 vccio6 6 - - vccio6 6 - - vccio6 6 - - r7 vccio6 6 - - vccio6 6 - - vccio6 6 - - h7 vccio7 7 - - vccio7 7 - - vccio7 7 - - j7 vccio7 7 - - vccio7 7 - - vccio7 7 - - k7 vccio7 7 - - vccio7 7 - - vccio7 7 - - l7 vccio7 7 - - vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. lfxp10, LFXP15 & lfxp20 logic signal connections: 388 fpbga (cont.) ball number lfxp10 LFXP15 lfxp20 ball function bank diff. dual function ball function bank diff. dual function ball function bank diff. dual function
4-43 pinout information lattice semiconductor latticexp family data sheet LFXP15 & lfxp20 logic signal connections: 484 fpbga ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function f5 programn 7 - - programn 7 - - e3 cclk 7 - - cclk 7 - - c1 pl2b 7 - - pl2b 7 - - - gndio7 7 - - gndio7 7 - - g5 pl3a 7 t 3 - pl3a 7 t 3 - g6 pl3b 7 c 3 - pl3b 7 c 3 - f4 pl4a 7 t - pl4a 7 t - f3 pl4b 7 c - pl4b 7 c - g4 pl5a 7 t 3 - pl5a 7 t 3 - g3 pl5b 7 c 3 - pl5b 7 c 3 - d1 pl6a 7 t 3 - pl6a 7 t 3 - d2 pl6b 7 c 3 - pl6b 7 c 3 - - gndio7 7 - - gndio7 7 - - e1 pl7a 7 t lum0_pllt_fb_a pl7a 7 t lum0_pllt_fb_a e2 pl7b 7 c lum0_pllc_fb_a pl7b 7 c lum0_pllc_fb_a h5 pl8a 7 t 3 - pl8a 7 t 3 - h6 pl8b 7 c 3 - pl8b 7 c 3 - h4 pl9a 7 - - pl9a 7 - - h3 pl10b 7 - vref1_7 pl10b 7 - vref1_7 f1 pl11a 7 t 3 dqs pl11a 7 t 3 dqs f2 pl11b 7 c 3 - pl11b 7 c 3 - - gndio7 7 - - gndio7 7 - - j5 pl12a 7 t - pl12a 7 t - j6 pl12b 7 c - pl12b 7 c - g1 pl13a 7 t 3 - pl13a 7 t 3 - g2 pl13b 7 c 3 - pl13b 7 c 3 - j4 pl15a 7 t 3 - pl15a 7 t 3 - j3 pl15b 7 c 3 - pl15b 7 c 3 - - gndio7 7 - - gndio7 7 - - h1 pl16a 7 t lum0_pllt_in_a pl16a 7 t lum0_pllt_in_a h2 pl16b 7 c lum0_pllc_in_a pl16b 7 c lum0_pllc_in_a j1 pl17a 7 t 3 - pl17a 7 t 3 - j2 pl17b 7 c 3 - pl17b 7 c 3 - k3 pl18a 7 - vref2_7 pl18a 7 - vref2_7 k2 pl19b 7 - - pl19b 7 - - k4 pl20a 7 t 3 dqs pl20a 7 t 3 dqs - gndio7 7 - - gndio7 7 - - k5 pl20b 7 c 3 - pl20b 7 c 3 - k1 pl21a 7 t - pl21a 7 t - l2 pl21b 7 c - pl21b 7 c - l4 pl22a 7 t 3 - pl22a 7 t 3 - l3 pl22b 7 c 3 - pl22b 7 c 3 -
4-44 pinout information lattice semiconductor latticexp family data sheet l1 - - - - pl23a 7 t 3 - m1 - - - - pl23b 7 c 3 - m2 - - - - pl24a 7 - - l5 vccp0 - - - vccp0 - - - n2 gndp0 - - - gndp0 - - - n1 - - - - pl25b 6 - - p2 - - - - pl26a 6 t 3 - p1 - - - - pl26b 6 c 3 - m4 pl23a 6 t 3 - pl27a 6 t 3 - m3 pl23b 6 c 3 - pl27b 6 c 3 - r2 pl24a 6 t pclkt6_0 pl28a 6 t pclkt6_0 - gndio6 6 - - gndio6 6 - - r1 pl24b 6 c pclkc6_0 pl28b 6 c pclkc6_0 n3 pl25a 6 t 3 - pl29a 6 t 3 - n4 pl25b 6 c 3 - pl29b 6 c 3 - m5 pl26a 6 - - pl30a 6 - - n5 pl27b 6 - vref1_6 pl31b 6 - vref1_6 t2 pl28a 6 t 3 dqs pl32a 6 t 3 dqs t1 pl28b 6 c 3 - pl32b 6 c 3 - - gndio6 6 - - gndio6 6 - - u2 pl29a 6 t llm0_pllt_in_a pl33a 6 t llm0_pllt_in_a u1 pl29b 6 c llm0_pllc_in_a pl33b 6 c llm0_pllc_in_a p3 pl30a 6 t 3 - pl34a 6 t 3 - p4 pl30b 6 c 3 - pl34b 6 c 3 - p6 pl32a 6 t 3 - pl36a 6 t 3 - p5 pl32b 6 c 3 - pl36b 6 c 3 - - gndio6 6 - - gndio6 6 - - v2 pl33a 6 t - pl37a 6 t - v1 pl33b 6 c - pl37b 6 c - w2 pl34a 6 t 3 - pl38a 6 t 3 - w1 pl34b 6 c 3 - pl38b 6 c 3 - r3 pl35a 6 - vref2_6 pl39a 6 - vref2_6 r4 pl36b 6 - - pl40b 6 - - r6 pl37a 6 t 3 dqs pl41a 6 t 3 dqs r5 pl37b 6 c 3 - pl41b 6 c 3 - - gndio6 6 - - gndio6 6 - - y2 pl38a 6 t llm0_pllt_fb_a pl42a 6 t llm0_pllt_fb_a y1 pl38b 6 c llm0_pllc_fb_a pl42b 6 c llm0_pllc_fb_a t3 pl39a 6 t 3 - pl43a 6 t 3 - t4 pl39b 6 c 3 - pl43b 6 c 3 - w3 pl40a 6 t 3 - pl44a 6 t 3 - v3 pl40b 6 c 3 - pl44b 6 c 3 - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-45 pinout information lattice semiconductor latticexp family data sheet t6 pl41a 6 t - pl45a 6 t - t5 pl41b 6 c - pl45b 6 c - - gndio6 6 - - gndio6 6 - - u3 pl42a 6 t 3 - pl46a 6 t 3 - u4 pl42b 6 c 3 - pl46b 6 c 3 - v4 pl43a 6 - - pl47a 6 - - w4 sleepn 1 / toe 2 -- - sleepn 1 / toe 2 -- - w5 initn 5 - - initn 5 - - y3 - - - - pb3b 5 - - - gndio5 5 - - gndio5 5 - - u5 - - - - pb4a 5 t - v5 - - - - pb4b 5 c - y4 - - - - pb5a 5 t - y5 - - - - pb5b 5 c - v6 - - - - pb6a 5 t - - gndio5 5 - - gndio5 5 - - u6 - - - - pb6b 5 c - w6 pb3a 5 t - pb7a 5 t - y6 pb3b 5 c - pb7b 5 c - aa2 pb4a 5 t - pb8a 5 t - aa3 pb4b 5 c - pb8b 5 c - v7 pb5a 5 - - pb9a 5 - - u7 pb6b 5 - - pb10b 5 - - y7 pb7a 5 t dqs pb11a 5 t dqs w7 pb7b 5 c - pb11b 5 c - aa4 pb8a 5 t - pb12a 5 t - - gndio5 5 - - gndio5 5 - - aa5 pb8b 5 c - pb12b 5 c - ab3 pb9a 5 t - pb13a 5 t - ab4 pb9b 5 c - pb13b 5 c - aa6 pb10a 5 t - pb14a 5 t - aa7 pb10b 5 c - pb14b 5 c - u8 pb11a 5 t - pb15a 5 t - v8 pb11b 5 c - pb15b 5 c - y8 pb12a 5 t vref1_5 pb16a 5 t vref1_5 - gndio5 5 - - gndio5 5 - - w8 pb12b 5 c - pb16b 5 c - v9 pb13a 5 - - pb17a 5 - - u9 pb14b 5 - - pb18b 5 - - y9 pb15a 5 t dqs pb19a 5 t dqs w9 pb15b 5 c - pb19b 5 c - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-46 pinout information lattice semiconductor latticexp family data sheet ab5 pb16a 5 t - pb20a 5 t - ab6 pb16b 5 c - pb20b 5 c - aa8 pb17a 5 t - pb21a 5 t - aa9 pb17b 5 c vref2_5 pb21b 5 c vref2_5 w10 pb18a 5 t - pb22a 5 t - - gndio5 5 - - gndio5 5 - - v10 pb18b 5 c - pb22b 5 c - ab7 pb19a 5 t - pb23a 5 t - ab8 pb19b 5 c - pb23b 5 c - ab9 pb20a 5 t - pb24a 5 t - ab10 pb20b 5 c - pb24b 5 c - y10 pb21a 5 - - pb25a 5 - - aa10 pb22b 5 - - pb26b 5 - - w11 pb23a 5 t dqs pb27a 5 t dqs v11 pb23b 5 c - pb27b 5 c - - gndio5 5 - - gndio5 5 - - y11 pb24a 5 t - pb28a 5 t - aa11 pb24b 5 c - pb28b 5 c - ab11 pb25a 5 t - pb29a 5 t - ab12 pb25b 5 c - pb29b 5 c - y12 pb26a 4 t - pb30a 4 t - aa12 pb26b 4 c - pb30b 4 c - w12 pb27a 4 t pclkt4_0 pb31a 4 t pclkt4_0 v12 pb27b 4 c pclkc4_0 pb31b 4 c pclkc4_0 - gndio4 4 - - gndio4 4 - - ab13 pb28a 4 t - pb32a 4 t - ab14 pb28b 4 c - pb32b 4 c - aa13 pb29a 4 - - pb33a 4 - - y13 pb30b 4 - - pb34b 4 - - ab15 pb31a 4 t dqs pb35a 4 t dqs ab16 pb31b 4 c vref1_4 pb35b 4 c vref1_4 v13 pb32a 4 t - pb36a 4 t - w13 pb32b 4 c - pb36b 4 c - aa14 pb33a 4 t - pb37a 4 t - - gndio4 4 - - gndio4 4 - - aa15 pb33b 4 c - pb37b 4 c - ab17 pb34a 4 t - pb38a 4 t - ab18 pb34b 4 c - pb38b 4 c - w14 pb35a 4 t - pb39a 4 t - y14 pb35b 4 c - pb39b 4 c - u14 pb36a 4 t vref2_4 pb40a 4 t vref2_4 v14 pb36b 4 c - pb40b 4 c - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-47 pinout information lattice semiconductor latticexp family data sheet ab19 pb37a 4 - - pb41a 4 - - ab20 pb38b 4 - - pb42b 4 - - - gndio4 4 - - gndio4 4 - - v15 pb39a 4 t dqs pb43a 4 t dqs u15 pb39b 4 c - pb43b 4 c - y15 pb40a 4 t - pb44a 4 t - w15 pb40b 4 c - pb44b 4 c - aa16 pb41a 4 t - pb45a 4 t - aa17 pb41b 4 c - pb45b 4 c - aa18 pb42a 4 t - pb46a 4 t - aa19 pb42b 4 c - pb46b 4 c - y16 pb43a 4 t - pb47a 4 t - w16 pb43b 4 c - pb47b 4 c - - gndio4 4 - - gndio4 4 - - aa20 pb44a 4 t - pb48a 4 t - aa21 pb44b 4 c - pb48b 4 c - y17 pb45a 4 - - pb49a 4 - - y18 pb46b 4 - - pb50b 4 - - y19 pb47a 4 t dqs pb51a 4 t dqs y20 pb47b 4 c - pb51b 4 c - v16 pb48a 4 t - pb52a 4 t - u16 pb48b 4 c - pb52b 4 c - - gndio4 4 - - gndio4 4 - - u18 - - - - pb53a 4 t - v18 - - - - pb53b 4 c - w19 - - - - pb54a 4 t - w18 - - - - pb54b 4 c - u17 - - - - pb55a 4 t - v17 - - - - pb55b 4 c - - gndio4 4 - - gndio4 4 - - w17 - - - - pb56a 4 - - - gndio3 3 - - gndio3 3 - - v19 pr43a 3 - - pr47a 3 - - u20 pr42b 3 c 3 - pr46b 3 c 3 - u19 pr42a 3 t 3 - pr46a 3 t 3 - v20 pr41b 3 c - pr45b 3 c - w20 pr41a 3 t - pr45a 3 t - t17 pr40b 3 c 3 - pr44b 3 c 3 - t18 pr40a 3 t 3 - pr44a 3 t 3 - t19 pr39b 3 c 3 - pr43b 3 c 3 - t20 pr39a 3 t 3 - pr43a 3 t 3 - - gndio3 3 - - gndio3 3 - - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-48 pinout information lattice semiconductor latticexp family data sheet r18 pr38b 3 c rlm0_pllc_fb_a pr42b 3 c rlm0_pllc_fb_a r17 pr38a 3 t rlm0_pllt_fb_a pr42a 3 t rlm0_pllt_fb_a y22 pr37b 3 c 3 - pr41b 3 c 3 - y21 pr37a 3 t 3 dqs pr41a 3 t 3 dqs w22 pr36b 3 - - pr40b 3 - - w21 pr35a 3 - vref1_3 pr39a 3 - vref1_3 p17 pr34b 3 c 3 - pr38b 3 c 3 - p18 pr34a 3 t 3 - pr38a 3 t 3 - - gndio3 3 - - gndio3 3 - - r19 pr33b 3 c - pr37b 3 c - r20 pr33a 3 t - pr37a 3 t - v22 pr32b 3 c 3 - pr36b 3 c 3 - v21 pr32a 3 t 3 - pr36a 3 t 3 - u22 pr30b 3 c 3 - pr34b 3 c 3 - u21 pr30a 3 t 3 - pr34a 3 t 3 - p19 pr29b 3 c rlm0_pllc_in_a pr33b 3 c rlm0_pllc_in_a p20 pr29a 3 t rlm0_pllt_in_a pr33a 3 t rlm0_pllt_in_a - gndio3 3 - - gndio3 3 - - t22 pr28b 3 c 3 - pr32b 3 c 3 - t21 pr28a 3 t 3 dqs pr32a 3 t 3 dqs r22 pr27b 3 - - pr31b 3 - - r21 pr26a 3 - vref2_3 pr30a 3 - vref2_3 n19 pr25b 3 c 3 - pr29b 3 c 3 - n20 pr25a 3 t 3 - pr29a 3 t 3 - n18 pr24b 3 c - pr28b 3 c - m18 pr24a 3 t - pr28a 3 t - - gndio3 3 - - gndio3 3 - - p22 pr23b 3 c 3 - pr27b 3 c 3 - p21 pr23a 3 t 3 - pr27a 3 t 3 - n22 - - - - pr26b 3 c 3 - n21 - - - - pr26a 3 t 3 - m19 - - - - pr25b 3 - - m20 gndp1 - - - gndp1 - - - l18 vccp1 - - - vccp1 - - - m21 - - - - pr24a 2 - - m22 pr22b 2 c 3 - pr23b 2 c 3 - l22 pr22a 2 t 3 - pr23a 2 t 3 - - gndio2 2 - - gndio2 2 - - l19 - - - - pr22b 2 c 3 - l20 - - - - pr22a 2 t 3 - l21 pr21b 2 c pclkc2_0 pr21b 2 c pclkc2_0 k22 pr21a 2 t pclkt2_0 pr21a 2 t pclkt2_0 LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-49 pinout information lattice semiconductor latticexp family data sheet j21 pr20b 2 c 3 - pr20b 2 c 3 - j22 pr20a 2 t 3 dqs pr20a 2 t 3 dqs k18 pr19b 2 - - pr19b 2 - - k19 pr18a 2 - vref1_2 pr18a 2 - vref1_2 - gndio2 2 - - gndio2 2 - - k21 pr17b 2 c 3 - pr17b 2 c 3 - k20 pr17a 2 t 3 - pr17a 2 t 3 - h21 pr16b 2 c rum0_pllc_in_a pr16b 2 c rum0_pllc_in_a h22 pr16a 2 t rum0_pllt_in_a pr16a 2 t rum0_pllt_in_a j20 pr15b 2 c 3 - pr15b 2 c 3 - j19 pr15a 2 t 3 - pr15a 2 t 3 - - gndio2 2 - - gndio2 2 - - j17 pr13b 2 c 3 - pr13b 2 c 3 - j18 pr13a 2 t 3 - pr13a 2 t 3 - g21 pr12b 2 c - pr12b 2 c - g22 pr12a 2 t - pr12a 2 t - f21 pr11b 2 c 3 - pr11b 2 c 3 - f22 pr11a 2 t 3 dqs pr11a 2 t 3 dqs - gndio2 2 - - gndio2 2 - - h20 pr10b 2 - - pr10b 2 - - h19 pr9a 2 - vref2_2 pr9a 2 - vref2_2 h17 pr8b 2 c 3 - pr8b 2 c 3 - h18 pr8a 2 t 3 - pr8a 2 t 3 - e21 pr7b 2 c rum0_pllc_fb_a pr7b 2 c rum0_pllc_fb_a e22 pr7a 2 t rum0_pllt_fb_a pr7a 2 t rum0_pllt_fb_a d21 pr6b 2 c 3 - pr6b 2 c 3 - d22 pr6a 2 t 3 - pr6a 2 t 3 - g20 pr5b 2 c 3 - pr5b 2 c 3 - g19 pr5a 2 t 3 - pr5a 2 t 3 - g17 pr4b 2 c - pr4b 2 c - g18 pr4a 2 t - pr4a 2 t - - gndio2 2 - - gndio2 2 - - f18 pr3b 2 c 3 - pr3b 2 c 3 - f19 pr3a 2 t 3 - pr3a 2 t 3 - c22 pr2b 2 - - pr2b 2 - - f20 tdo - - - tdo - - - e20 vccj - - - vccj - - - d19 tdi - - - tdi - - - e19 tms - - - tms - - - d20 tck - - - tck - - - c20 - - - - pt56a 1 - - - gndio1 1 - - gndio1 1 - - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-50 pinout information lattice semiconductor latticexp family data sheet d18 - - - - pt55b 1 c - e18 - - - - pt55a 1 t - c19 - - - - pt54b 1 c - c18 - - - - pt54a 1 t - c21 - - - - pt53b 1 c - - gndio1 1 - - gndio1 1 - - b21 - - - - pt53a 1 t - e17 pt48b 1 c - pt52b 1 c - e16 pt48a 1 t - pt52a 1 t - c17 pt47b 1 c - pt51b 1 c - d17 pt47a 1 t dqs pt51a 1 t dqs f17 pt46b 1 - - pt50b 1 - - f16 pt45a 1 - - pt49a 1 - - c16 pt44b 1 c - pt48b 1 c - d16 pt44a 1 t - pt48a 1 t - a20 pt43b 1 c - pt47b 1 c - - gndio1 1 - - gndio1 1 - - b20 pt43a 1 t - pt47a 1 t - a19 pt42b 1 c - pt46b 1 c - b19 pt42a 1 t - pt46a 1 t - c15 pt41b 1 c - pt45b 1 c - d15 pt41a 1 t - pt45a 1 t - a18 pt40b 1 c - pt44b 1 c - b18 pt40a 1 t - pt44a 1 t - f15 pt39b 1 c vref1_1 pt43b 1 c vref1_1 - gndio1 1 - - gndio1 1 - - e15 pt39a 1 t dqs pt43a 1 t dqs a17 pt38b 1 - - pt42b 1 - - b17 pt37a 1 - - pt41a 1 - - e14 pt36b 1 c - pt40b 1 c - f14 pt36a 1 t - pt40a 1 t - d14 pt35b 1 c - pt39b 1 c - c14 pt35a 1 t d0 pt39a 1 t d0 a16 pt34b 1 c d1 pt38b 1 c d1 b16 pt34a 1 t vref2_1 pt38a 1 t vref2_1 a15 pt33b 1 c - pt37b 1 c - b15 pt33a 1 t d2 pt37a 1 t d2 - gndio1 1 - - gndio1 1 - - e13 pt32b 1 c d3 pt36b 1 c d3 d13 pt32a 1 t - pt36a 1 t - c13 pt31b 1 c - pt35b 1 c - b13 pt31a 1 t dqs pt35a 1 t dqs LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-51 pinout information lattice semiconductor latticexp family data sheet a14 pt30b 1 - - pt34b 1 - - b14 pt29a 1 - d4 pt33a 1 - d4 c12 pt28b 1 c - pt32b 1 c - b12 pt28a 1 t d5 pt32a 1 t d5 - gndio1 1 - - gndio1 1 - - d12 pt27b 1 c d6 pt31b 1 c d6 e12 pt27a 1 t - pt31a 1 t - a13 pt26b 1 c d7 pt30b 1 c d7 a12 pt26a 1 t - pt30a 1 t - a11 pt25b 0 c busy pt29b 0 c busy - gndio0 0 - - gndio0 0 - - a10 pt25a 0 t cs1n pt29a 0 t cs1n d11 pt24b 0 c pclkc0_0 pt28b 0 c pclkc0_0 e11 pt24a 0 t pclkt0_0 pt28a 0 t pclkt0_0 b11 pt23b 0 c - pt27b 0 c - c11 pt23a 0 t dqs pt27a 0 t dqs b9 pt22b 0 - - pt26b 0 - - a9 pt21a 0 - dout pt25a 0 - dout b8 pt20b 0 c - pt24b 0 c - - gndio0 0 - - gndio0 0 - - a8 pt20a 0 t writen pt24a 0 t writen e10 pt19b 0 c - pt23b 0 c - d10 pt19a 0 t vref1_0 pt23a 0 t vref1_0 c10 pt18b 0 c - pt22b 0 c - b10 pt18a 0 t di pt22a 0 t di b7 pt17b 0 c - pt21b 0 c - a7 pt17a 0 t csn pt21a 0 t csn c9 pt16b 0 c - pt20b 0 c - d9 pt16a 0 t - pt20a 0 t - b6 pt15b 0 c vref2_0 pt19b 0 c vref2_0 a6 pt15a 0 t dqs pt19a 0 t dqs f9 pt14b 0 - - pt18b 0 - - e9 pt13a 0 - - pt17a 0 - - - gndio0 0 - - gndio0 0 - - b5 pt12b 0 c - pt16b 0 c - a5 pt12a 0 t - pt16a 0 t - c8 pt11b 0 c - pt15b 0 c - d8 pt11a 0 t - pt15a 0 t - b4 pt10b 0 c - pt14b 0 c - a4 pt10a 0 t - pt14a 0 t - f8 pt9b 0 c - pt13b 0 c - e8 pt9a 0 t - pt13a 0 t - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-52 pinout information lattice semiconductor latticexp family data sheet b3 pt8b 0 c - pt12b 0 c - a3 pt8a 0 t - pt12a 0 t - - gndio0 0 - - gndio0 0 - - d7 pt7b 0 c - pt11b 0 c - c7 pt7a 0 t dqs pt11a 0 t dqs b2 pt6b 0 - - pt10b 0 - - c2 pt5a 0 - - pt9a 0 - - c3 pt4b 0 c - pt8b 0 c - d3 pt4a 0 t - pt8a 0 t - f7 pt3b 0 c - pt7b 0 c - e7 pt3a 0 t - pt7a 0 t - - gndio0 0 - - gndio0 0 - - c6 - - - - pt6b 0 c - d6 - - - - pt6a 0 t - c5 - - - - pt5b 0 c - c4 - - - - pt5a 0 t - f6 - - - - pt4b 0 c - e6 - - - - pt4a 0 t - - gndio0 0 - - gndio0 0 - - e4 - - - - pt3b 0 - - e5 cfg0 0 - - cfg0 0 - - d4 cfg1 0 - - cfg1 0 - - d5 done 0 - - done 0 - - a1 gnd - - - gnd - - - a2 gnd - - - gnd - - - a21 gnd - - - gnd - - - a22 gnd - - - gnd - - - aa1 gnd - - - gnd - - - aa22 gnd - - - gnd - - - ab1 gnd - - - gnd - - - ab2 gnd - - - gnd - - - ab21 gnd - - - gnd - - - ab22 gnd - - - gnd - - - b1 gnd - - - gnd - - - b22 gnd - - - gnd - - - h14 gnd - - - gnd - - - h9 gnd - - - gnd - - - j10 gnd - - - gnd - - - j11 gnd - - - gnd - - - j12 gnd - - - gnd - - - j13 gnd - - - gnd - - - j14 gnd - - - gnd - - - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-53 pinout information lattice semiconductor latticexp family data sheet j15 gnd - - - gnd - - - j8 gnd - - - gnd - - - j9 gnd - - - gnd - - - k10 gnd - - - gnd - - - k11 gnd - - - gnd - - - k12 gnd - - - gnd - - - k13 gnd - - - gnd - - - k14 gnd - - - gnd - - - k9 gnd - - - gnd - - - l10 gnd - - - gnd - - - l11 gnd - - - gnd - - - l12 gnd - - - gnd - - - l13 gnd - - - gnd - - - l14 gnd - - - gnd - - - l9 gnd - - - gnd - - - m10 gnd - - - gnd - - - m11 gnd - - - gnd - - - m12 gnd - - - gnd - - - m13 gnd - - - gnd - - - m14 gnd - - - gnd - - - m9 gnd - - - gnd - - - n10 gnd - - - gnd - - - n11 gnd - - - gnd - - - n12 gnd - - - gnd - - - n13 gnd - - - gnd - - - n14 gnd - - - gnd - - - n9 gnd - - - gnd - - - p10 gnd - - - gnd - - - p11 gnd - - - gnd - - - p12 gnd - - - gnd - - - p13 gnd - - - gnd - - - p14 gnd - - - gnd - - - p15 gnd - - - gnd - - - p8 gnd - - - gnd - - - p9 gnd - - - gnd - - - r14 gnd - - - gnd - - - r9 gnd - - - gnd - - - f10 vcc - - - vcc - - - f13 vcc - - - vcc - - - g10 vcc - - - vcc - - - g13 vcc - - - vcc - - - g14 vcc - - - vcc - - - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-54 pinout information lattice semiconductor latticexp family data sheet g9 vcc - - - vcc - - - h15 vcc - - - vcc - - - h8 vcc - - - vcc - - - j16 vcc - - - vcc - - - j7 vcc - - - vcc - - - k16 vcc - - - vcc - - - k17 vcc - - - vcc - - - k6 vcc - - - vcc - - - k7 vcc - - - vcc - - - n16 vcc - - - vcc - - - n17 vcc - - - vcc - - - n6 vcc - - - vcc - - - n7 vcc - - - vcc - - - p16 vcc - - - vcc - - - p7 vcc - - - vcc - - - r15 vcc - - - vcc - - - r8 vcc - - - vcc - - - t10 vcc - - - vcc - - - t13 vcc - - - vcc - - - t14 vcc - - - vcc - - - t9 vcc - - - vcc - - - u10 vcc - - - vcc - - - u13 vcc - - - vcc - - - g15 vccaux - - - vccaux - - - g16 vccaux - - - vccaux - - - g7 vccaux - - - vccaux - - - g8 vccaux - - - vccaux - - - h16 vccaux - - - vccaux - - - h7 vccaux - - - vccaux - - - r16 vccaux - - - vccaux - - - r7 vccaux - - - vccaux - - - t15 vccaux - - - vccaux - - - t16 vccaux - - - vccaux - - - t7 vccaux - - - vccaux - - - t8 vccaux - - - vccaux - - - f11 vccio0 0 - - vccio0 0 - - g11 vccio0 0 - - vccio0 0 - - h10 vccio0 0 - - vccio0 0 - - h11 vccio0 0 - - vccio0 0 - - f12 vccio1 1 - - vccio1 1 - - g12 vccio1 1 - - vccio1 1 - - h12 vccio1 1 - - vccio1 1 - - LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-55 pinout information lattice semiconductor latticexp family data sheet h13 vccio1 1 - - vccio1 1 - - k15 vccio2 2 - - vccio2 2 - - l15 vccio2 2 - - vccio2 2 - - l16 vccio2 2 - - vccio2 2 - - l17 vccio2 2 - - vccio2 2 - - m15 vccio3 3 - - vccio3 3 - - m16 vccio3 3 - - vccio3 3 - - m17 vccio3 3 - - vccio3 3 - - n15 vccio3 3 - - vccio3 3 - - r12 vccio4 4 - - vccio4 4 - - r13 vccio4 4 - - vccio4 4 - - t12 vccio4 4 - - vccio4 4 - - u12 vccio4 4 - - vccio4 4 - - r10 vccio5 5 - - vccio5 5 - - r11 vccio5 5 - - vccio5 5 - - t11 vccio5 5 - - vccio5 5 - - u11 vccio5 5 - - vccio5 5 - - m6 vccio6 6 - - vccio6 6 - - m7 vccio6 6 - - vccio6 6 - - m8 vccio6 6 - - vccio6 6 - - n8 vccio6 6 - - vccio6 6 - - k8 vccio7 7 - - vccio7 7 - - l6 vccio7 7 - - vccio7 7 - - l7 vccio7 7 - - vccio7 7 - - l8 vccio7 7 - - vccio7 7 - - 1. applies to lfxp ? only. 2. applies to lfxp ? only. 3. supports dedicated lvds outputs. LFXP15 & lfxp20 logic signal connections: 484 fpbga (cont.) ball number LFXP15 lfxp20 ball function bank differential dual function ball function bank differential dual function
4-56 pinout information lattice semiconductor latticexp family data sheet thermal management thermal management is recommended as part of any sound fpga design methodology. to assess the thermal characteristics of a system, lattice speci?s a maximum allowable junction temperature in all device data sheets. designers must complete a thermal analysis of their speci? design to ensure that the device and package do not exceed the junction temperature limits. refer to the thermal management document to ?d the device/package speci? thermal values. for further information for further information regarding thermal management, refer to the following located on the lattice website at www .latticesemi.com . thermal management document technical note tn1052 - power estimation and management for latticeecp/ec and latticexp devices power calculator tool included with lattices isplever design tool, or as a standalone download from www .latticesemi.com/softw are
december 2005 data sheet ds1001 ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 5-1 ds1001 ordering information_03.0 part number description ordering information (contact factory for speci? device availability) note: latticexp devices are dual marked. for example, the commercial speed grade lfxp10e-4f256c is also marked with industrial grade -3i (lfxp10e-3f256i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade does not have industrial markings. the markings appear as follows: lfxp xx x ?x xxxxxx x grade c = commercial i = industrial logic capacity 3k luts = 3 6k luts = 6 10k luts = 10 15k luts = 15 20k luts = 20 note: parts dual marked per table below. supply voltage c = 1.8v/2.5v/3.3v e = 1.2v speed 3 = slowest 4 5 = fastest package t100 = 100-pin tqfp t144 = 144-pin tqfp q208 = 208-pin pqfp f256 = 256-ball fpbga f388 = 388-ball fpbga f484 = 484-ball fpbga tn100 = 100-pin lead-free tqfp tn144 = 144-pin lead-free tqfp qn208 = 208-pin lead-free pqfp fn256 = 256-ball lead-free fpbga fn388 = 388-ball lead-free fpbga fn484 = 484-ball lead-free fpbga device family latticexp fpga lfxp10e- 4f256c-3i datecode latticexp family data sheet ordering information
5-2 ordering information lattice semiconductor latticexp family data sheet conventional packaging commercial part number i/os voltage grade package pins temp. luts lfxp3c-3q208c 136 1.8/2.5/3.3v -3 pqfp 208 com 3.1k lfxp3c-4q208c 136 1.8/2.5/3.3v -4 pqfp 208 com 3.1k lfxp3c-5q208c 136 1.8/2.5/3.3v -5 pqfp 208 com 3.1k lfxp3c-3t144c 100 1.8/2.5/3.3v -3 tqfp 144 com 3.1k lfxp3c-4t144c 100 1.8/2.5/3.3v -4 tqfp 144 com 3.1k lfxp3c-5t144c 100 1.8/2.5/3.3v -5 tqfp 144 com 3.1k lfxp3c-3t100c 62 1.8/2.5/3.3v -3 tqfp 100 com 3.1k lfxp3c-4t100c 62 1.8/2.5/3.3v -4 tqfp 100 com 3.1k lfxp3c-5t100c 62 1.8/2.5/3.3v -5 tqfp 100 com 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 5.8k lfxp6c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 5.8k lfxp6c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 5.8k lfxp6c-3q208c 142 1.8/2.5/3.3v -3 pqfp 208 com 5.8k lfxp6c-4q208c 142 1.8/2.5/3.3v -4 pqfp 208 com 5.8k lfxp6c-5q208c 142 1.8/2.5/3.3v -5 pqfp 208 com 5.8k lfxp6c-3t144c 100 1.8/2.5/3.3v -3 tqfp 144 com 5.8k lfxp6c-4t144c 100 1.8/2.5/3.3v -4 tqfp 144 com 5.8k lfxp6c-5t144c 100 1.8/2.5/3.3v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10c-3f388c 244 1.8/2.5/3.3v -3 fpbga 388 com 9.7k lfxp10c-4f388c 244 1.8/2.5/3.3v -4 fpbga 388 com 9.7k lfxp10c-5f388c 244 1.8/2.5/3.3v -5 fpbga 388 com 9.7k lfxp10c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 9.7k lfxp10c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 9.7k lfxp10c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 9.7k
5-3 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) part number i/os voltage grade package pins temp. luts LFXP15c-3f484c 300 1.8/2.5/3.3v -3 fpbga 484 com 15.5k LFXP15c-4f484c 300 1.8/2.5/3.3v -4 fpbga 484 com 15.5k LFXP15c-5f484c 300 1.8/2.5/3.3v -5 fpbga 484 com 15.5k LFXP15c-3f388c 268 1.8/2.5/3.3v -3 fpbga 388 com 15.5k LFXP15c-4f388c 268 1.8/2.5/3.3v -4 fpbga 388 com 15.5k LFXP15c-5f388c 268 1.8/2.5/3.3v -5 fpbga 388 com 15.5k LFXP15c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 15.5k LFXP15c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 15.5k LFXP15c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 15.5k part number i/os voltage grade package pins temp. luts lfxp20c-3f484c 340 1.8/2.5/3.3v -3 fpbga 484 com 19.7k lfxp20c-4f484c 340 1.8/2.5/3.3v -4 fpbga 484 com 19.7k lfxp20c-5f484c 340 1.8/2.5/3.3v -5 fpbga 484 com 19.7k lfxp20c-3f388c 268 1.8/2.5/3.3v -3 fpbga 388 com 19.7k lfxp20c-4f388c 268 1.8/2.5/3.3v -4 fpbga 388 com 19.7k lfxp20c-5f388c 268 1.8/2.5/3.3v -5 fpbga 388 com 19.7k lfxp20c-3f256c 188 1.8/2.5/3.3v -3 fpbga 256 com 19.7k lfxp20c-4f256c 188 1.8/2.5/3.3v -4 fpbga 256 com 19.7k lfxp20c-5f256c 188 1.8/2.5/3.3v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3q208c 136 1.2v -3 pqfp 208 com 3.1k lfxp3e-4q208c 136 1.2v -4 pqfp 208 com 3.1k lfxp3e-5q208c 136 1.2v -5 pqfp 208 com 3.1k lfxp3e-3t144c 100 1.2v -3 tqfp 144 com 3.1k lfxp3e-4t144c 100 1.2v -4 tqfp 144 com 3.1k lfxp3e-5t144c 100 1.2v -5 tqfp 144 com 3.1k lfxp3e-3t100c 62 1.2v -3 tqfp 100 com 3.1k lfxp3e-4t100c 62 1.2v -4 tqfp 100 com 3.1k lfxp3e-5t100c 62 1.2v -5 tqfp 100 com 3.1k
5-4 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) part number i/os voltage grade package pins temp. luts lfxp6e-3f256c 188 1.2v -3 fpbga 256 com 5.8k lfxp6e-4f256c 188 1.2v -4 fpbga 256 com 5.8k lfxp6e-5f256c 188 1.2v -5 fpbga 256 com 5.8k lfxp6e-3q208c 142 1.2v -3 pqfp 208 com 5.8k lfxp6e-4q208c 142 1.2v -4 pqfp 208 com 5.8k lfxp6e-5q208c 142 1.2v -5 pqfp 208 com 5.8k lfxp6e-3t144c 100 1.2v -3 tqfp 144 com 5.8k lfxp6e-4t144c 100 1.2v -4 tqfp 144 com 5.8k lfxp6e-5t144c 100 1.2v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10e-3f388c 244 1.2v -3 fpbga 388 com 9.7k lfxp10e-4f388c 244 1.2v -4 fpbga 388 com 9.7k lfxp10e-5f388c 244 1.2v -5 fpbga 388 com 9.7k lfxp10e-3f256c 188 1.2v -3 fpbga 256 com 9.7k lfxp10e-4f256c 188 1.2v -4 fpbga 256 com 9.7k lfxp10e-5f256c 188 1.2v -5 fpbga 256 com 9.7k part number i/os voltage grade package pins temp. luts LFXP15e-3f484c 300 1.2v -3 fpbga 484 com 15.5k LFXP15e-4f484c 300 1.2v -4 fpbga 484 com 15.5k LFXP15e-5f484c 300 1.2v -5 fpbga 484 com 15.5k LFXP15e-3f388c 268 1.2v -3 fpbga 388 com 15.5k LFXP15e-4f388c 268 1.2v -4 fpbga 388 com 15.5k LFXP15e-5f388c 268 1.2v -5 fpbga 388 com 15.5k LFXP15e-3f256c 188 1.2v -3 fpbga 256 com 15.5k LFXP15e-4f256c 188 1.2v -4 fpbga 256 com 15.5k LFXP15e-5f256c 188 1.2v -5 fpbga 256 com 15.5k
5-5 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) industrial part number i/os voltage grade package pins temp. luts lfxp20e-3f484c 340 1.2v -3 fpbga 484 com 19.7k lfxp20e-4f484c 340 1.2v -4 fpbga 484 com 19.7k lfxp20e-5f484c 340 1.2v -5 fpbga 484 com 19.7k lfxp20e-3f388c 268 1.2v -3 fpbga 388 com 19.7k lfxp20e-4f388c 268 1.2v -4 fpbga 388 com 19.7k lfxp20e-5f388c 268 1.2v -5 fpbga 388 com 19.7k lfxp20e-3f256c 188 1.2v -3 fpbga 256 com 19.7k lfxp20e-4f256c 188 1.2v -4 fpbga 256 com 19.7k lfxp20e-5f256c 188 1.2v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3c-3q208i 136 1.8/2.5/3.3v -3 pqfp 208 ind 3.1k lfxp3c-4q208i 136 1.8/2.5/3.3v -4 pqfp 208 ind 3.1k lfxp3c-3t144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 3.1k lfxp3c-4t144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 3.1k lfxp3c-3t100i 62 1.8/2.5/3.3v -3 tqfp 100 ind 3.1k lfxp3c-4t100i 62 1.8/2.5/3.3v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 5.8k lfxp6c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 5.8k lfxp6c-3q208i 142 1.8/2.5/3.3v -3 pqfp 208 ind 5.8k lfxp6c-4q208i 142 1.8/2.5/3.3v -4 pqfp 208 ind 5.8k lfxp6c-3t144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 5.8k lfxp6c-4t144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 5.8k part number i/os voltage grade package pins temp. luts lfxp10c-3f388i 244 1.8/2.5/3.3v -3 fpbga 388 ind 9.7k lfxp10c-4f388i 244 1.8/2.5/3.3v -4 fpbga 388 ind 9.7k lfxp10c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 9.7k lfxp10c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 9.7k
5-6 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts LFXP15c-3f484i 300 1.8/2.5/3.3v -3 fpbga 484 ind 15.5k LFXP15c-4f484i 300 1.8/2.5/3.3v -4 fpbga 484 ind 15.5k LFXP15c-3f388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 15.5k LFXP15c-4f388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 15.5k LFXP15c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 15.5k LFXP15c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20c-3f484i 340 1.8/2.5/3.3v -3 fpbga 484 ind 19.7k lfxp20c-4f484i 340 1.8/2.5/3.3v -4 fpbga 484 ind 19.7k lfxp20c-3f388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 19.7k lfxp20c-4f388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 19.7k lfxp20c-3f256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 19.7k lfxp20c-4f256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3q208i 136 1.2v -3 pqfp 208 ind 3.1k lfxp3e-4q208i 136 1.2v -4 pqfp 208 ind 3.1k lfxp3e-3t144i 100 1.2v -3 tqfp 144 ind 3.1k lfxp3e-4t144i 100 1.2v -4 tqfp 144 ind 3.1k lfxp3e-3t100i 62 1.2v -3 tqfp 100 ind 3.1k lfxp3e-4t100i 62 1.2v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6e-3f256i 188 1.2v -3 fpbga 256 ind 5.8k lfxp6e-4f256i 188 1.2v -4 fpbga 256 ind 5.8k lfxp6e-3q208i 142 1.2v -3 pqfp 208 ind 5.8k lfxp6e-4q208i 142 1.2v -4 pqfp 208 ind 5.8k lfxp6e-3t144i 100 1.2v -3 tqfp 144 ind 5.8k lfxp6e-4t144i 100 1.2v -4 tqfp 144 ind 5.8k part number i/os voltage grade package pins temp. luts lfxp10e-3f388i 244 1.2v -3 fpbga 388 ind 9.7k lfxp10e-4f388i 244 1.2v -4 fpbga 388 ind 9.7k lfxp10e-3f256i 188 1.2v -3 fpbga 256 ind 9.7k lfxp10e-4f256i 188 1.2v -4 fpbga 256 ind 9.7k
5-7 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts LFXP15e-3f484i 300 1.2v -3 fpbga 484 ind 15.5k LFXP15e-4f484i 300 1.2v -4 fpbga 484 ind 15.5k LFXP15e-3f388i 268 1.2v -3 fpbga 388 ind 15.5k LFXP15e-4f388i 268 1.2v -4 fpbga 388 ind 15.5k LFXP15e-3f256i 188 1.2v -3 fpbga 256 ind 15.5k LFXP15e-4f256i 188 1.2v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20e-3f484i 340 1.2v -3 fpbga 484 ind 19.7k lfxp20e-4f484i 340 1.2v -4 fpbga 484 ind 19.7k lfxp20e-3f388i 268 1.2v -3 fpbga 388 ind 19.7k lfxp20e-4f388i 268 1.2v -4 fpbga 388 ind 19.7k lfxp20e-3f256i 188 1.2v -3 fpbga 256 ind 19.7k lfxp20e-4f256i 188 1.2v -4 fpbga 256 ind 19.7k
5-8 ordering information lattice semiconductor latticexp family data sheet lead-free packaging commercial part number i/os voltage grade package pins temp. luts lfxp3c-3qn208c 136 1.8/2.5/3.3v -3 pqfp 208 com 3.1k lfxp3c-4qn208c 136 1.8/2.5/3.3v -4 pqfp 208 com 3.1k lfxp3c-5qn208c 136 1.8/2.5/3.3v -5 pqfp 208 com 3.1k lfxp3c-3tn144c 100 1.8/2.5/3.3v -3 tqfp 144 com 3.1k lfxp3c-4tn144c 100 1.8/2.5/3.3v -4 tqfp 144 com 3.1k lfxp3c-5tn144c 100 1.8/2.5/3.3v -5 tqfp 144 com 3.1k lfxp3c-3tn100c 62 1.8/2.5/3.3v -3 tqfp 100 com 3.1k lfxp3c-4tn100c 62 1.8/2.5/3.3v -4 tqfp 100 com 3.1k lfxp3c-5tn100c 62 1.8/2.5/3.3v -5 tqfp 100 com 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 5.8k lfxp6c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 5.8k lfxp6c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 5.8k lfxp6c-3qn208c 142 1.8/2.5/3.3v -3 pqfp 208 com 5.8k lfxp6c-4qn208c 142 1.8/2.5/3.3v -4 pqfp 208 com 5.8k lfxp6c-5qn208c 142 1.8/2.5/3.3v -5 pqfp 208 com 5.8k lfxp6c-3tn144c 100 1.8/2.5/3.3v -3 tqfp 144 com 5.8k lfxp6c-4tn144c 100 1.8/2.5/3.3v -4 tqfp 144 com 5.8k lfxp6c-5tn144c 100 1.8/2.5/3.3v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10c-3fn388c 244 1.8/2.5/3.3v -3 fpbga 388 com 9.7k lfxp10c-4fn388c 244 1.8/2.5/3.3v -4 fpbga 388 com 9.7k lfxp10c-5fn388c 244 1.8/2.5/3.3v -5 fpbga 388 com 9.7k lfxp10c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 9.7k lfxp10c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 9.7k lfxp10c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 9.7k part number i/os voltage grade package pins temp. luts LFXP15c-3fn484c 300 1.8/2.5/3.3v -3 fpbga 484 com 15.5k LFXP15c-4fn484c 300 1.8/2.5/3.3v -4 fpbga 484 com 15.5k LFXP15c-5fn484c 300 1.8/2.5/3.3v -5 fpbga 484 com 15.5k LFXP15c-3fn388c 268 1.8/2.5/3.3v -3 fpbga 388 com 15.5k LFXP15c-4fn388c 268 1.8/2.5/3.3v -4 fpbga 388 com 15.5k LFXP15c-5fn388c 268 1.8/2.5/3.3v -5 fpbga 388 com 15.5k LFXP15c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 15.5k LFXP15c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 15.5k LFXP15c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 15.5k
5-9 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) part number i/os voltage grade package pins temp. luts lfxp20c-3fn484c 340 1.8/2.5/3.3v -3 fpbga 484 com 19.7k lfxp20c-4fn484c 340 1.8/2.5/3.3v -4 fpbga 484 com 19.7k lfxp20c-5fn484c 340 1.8/2.5/3.3v -5 fpbga 484 com 19.7k lfxp20c-3fn388c 268 1.8/2.5/3.3v -3 fpbga 388 com 19.7k lfxp20c-4fn388c 268 1.8/2.5/3.3v -4 fpbga 388 com 19.7k lfxp20c-5fn388c 268 1.8/2.5/3.3v -5 fpbga 388 com 19.7k lfxp20c-3fn256c 188 1.8/2.5/3.3v -3 fpbga 256 com 19.7k lfxp20c-4fn256c 188 1.8/2.5/3.3v -4 fpbga 256 com 19.7k lfxp20c-5fn256c 188 1.8/2.5/3.3v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3qn208c 136 1.2v -3 pqfp 208 com 3.1k lfxp3e-4qn208c 136 1.2v -4 pqfp 208 com 3.1k lfxp3e-5qn208c 136 1.2v -5 pqfp 208 com 3.1k lfxp3e-3tn144c 100 1.2v -3 tqfp 144 com 3.1k lfxp3e-4tn144c 100 1.2v -4 tqfp 144 com 3.1k lfxp3e-5tn144c 100 1.2v -5 tqfp 144 com 3.1k lfxp3e-3tn100c 62 1.2v -3 tqfp 100 com 3.1k lfxp3e-4tn100c 62 1.2v -4 tqfp 100 com 3.1k lfxp3e-5tn100c 62 1.2v -5 tqfp 100 com 3.1k part number i/os voltage grade package pins temp. luts lfxp6e-3fn256c 188 1.2v -3 fpbga 256 com 5.8k lfxp6e-4fn256c 188 1.2v -4 fpbga 256 com 5.8k lfxp6e-5fn256c 188 1.2v -5 fpbga 256 com 5.8k lfxp6e-3qn208c 142 1.2v -3 pqfp 208 com 5.8k lfxp6e-4qn208c 142 1.2v -4 pqfp 208 com 5.8k lfxp6e-5qn208c 142 1.2v -5 pqfp 208 com 5.8k lfxp6e-3tn144c 100 1.2v -3 tqfp 144 com 5.8k lfxp6e-4tn144c 100 1.2v -4 tqfp 144 com 5.8k lfxp6e-5tn144c 100 1.2v -5 tqfp 144 com 5.8k part number i/os voltage grade package pins temp. luts lfxp10e-3fn388c 244 1.2v -3 fpbga 388 com 9.7k lfxp10e-4fn388c 244 1.2v -4 fpbga 388 com 9.7k lfxp10e-5fn388c 244 1.2v -5 fpbga 388 com 9.7k lfxp10e-3fn256c 188 1.2v -3 fpbga 256 com 9.7k lfxp10e-4fn256c 188 1.2v -4 fpbga 256 com 9.7k lfxp10e-5fn256c 188 1.2v -5 fpbga 256 com 9.7k
5-10 ordering information lattice semiconductor latticexp family data sheet commercial (cont.) industrial part number i/os voltage grade package pins temp. luts LFXP15e-3fn484c 300 1.2v -3 fpbga 484 com 15.5k LFXP15e-4fn484c 300 1.2v -4 fpbga 484 com 15.5k LFXP15e-5fn484c 300 1.2v -5 fpbga 484 com 15.5k LFXP15e-3fn388c 268 1.2v -3 fpbga 388 com 15.5k LFXP15e-4fn388c 268 1.2v -4 fpbga 388 com 15.5k LFXP15e-5fn388c 268 1.2v -5 fpbga 388 com 15.5k LFXP15e-3fn256c 188 1.2v -3 fpbga 256 com 15.5k LFXP15e-4fn256c 188 1.2v -4 fpbga 256 com 15.5k LFXP15e-5fn256c 188 1.2v -5 fpbga 256 com 15.5k part number i/os voltage grade package pins temp. luts lfxp20e-3fn484c 340 1.2v -3 fpbga 484 com 19.7k lfxp20e-4fn484c 340 1.2v -4 fpbga 484 com 19.7k lfxp20e-5fn484c 340 1.2v -5 fpbga 484 com 19.7k lfxp20e-3fn388c 268 1.2v -3 fpbga 388 com 19.7k lfxp20e-4fn388c 268 1.2v -4 fpbga 388 com 19.7k lfxp20e-5fn388c 268 1.2v -5 fpbga 388 com 19.7k lfxp20e-3fn256c 188 1.2v -3 fpbga 256 com 19.7k lfxp20e-4fn256c 188 1.2v -4 fpbga 256 com 19.7k lfxp20e-5fn256c 188 1.2v -5 fpbga 256 com 19.7k part number i/os voltage grade package pins temp. luts lfxp3c-3qn208i 136 1.8/2.5/3.3v -3 pqfp 208 ind 3.1k lfxp3c-4qn208i 136 1.8/2.5/3.3v -4 pqfp 208 ind 3.1k lfxp3c-3tn144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 3.1k lfxp3c-4tn144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 3.1k lfxp3c-3tn100i 62 1.8/2.5/3.3v -3 tqfp 100 ind 3.1k lfxp3c-4tn100i 62 1.8/2.5/3.3v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 5.8k lfxp6c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 5.8k lfxp6c-3qn208i 142 1.8/2.5/3.3v -3 pqfp 208 ind 5.8k lfxp6c-4qn208i 142 1.8/2.5/3.3v -4 pqfp 208 ind 5.8k lfxp6c-3tn144i 100 1.8/2.5/3.3v -3 tqfp 144 ind 5.8k lfxp6c-4tn144i 100 1.8/2.5/3.3v -4 tqfp 144 ind 5.8k
5-11 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts lfxp10c-3fn388i 244 1.8/2.5/3.3v -3 fpbga 388 ind 9.7k lfxp10c-4fn388i 244 1.8/2.5/3.3v -4 fpbga 388 ind 9.7k lfxp10c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 9.7k lfxp10c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 9.7k part number i/os voltage grade package pins temp. luts LFXP15c-3fn484i 300 1.8/2.5/3.3v -3 fpbga 484 ind 15.5k LFXP15c-4fn484i 300 1.8/2.5/3.3v -4 fpbga 484 ind 15.5k LFXP15c-3fn388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 15.5k LFXP15c-4fn388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 15.5k LFXP15c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 15.5k LFXP15c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20c-3fn484i 340 1.8/2.5/3.3v -3 fpbga 484 ind 19.7k lfxp20c-4fn484i 340 1.8/2.5/3.3v -4 fpbga 484 ind 19.7k lfxp20c-3fn388i 268 1.8/2.5/3.3v -3 fpbga 388 ind 19.7k lfxp20c-4fn388i 268 1.8/2.5/3.3v -4 fpbga 388 ind 19.7k lfxp20c-3fn256i 188 1.8/2.5/3.3v -3 fpbga 256 ind 19.7k lfxp20c-4fn256i 188 1.8/2.5/3.3v -4 fpbga 256 ind 19.7k part number i/os voltage grade package pins temp. luts lfxp3e-3qn208i 136 1.2v -3 pqfp 208 ind 3.1k lfxp3e-4qn208i 136 1.2v -4 pqfp 208 ind 3.1k lfxp3e-3tn144i 100 1.2v -3 tqfp 144 ind 3.1k lfxp3e-4tn144i 100 1.2v -4 tqfp 144 ind 3.1k lfxp3e-3tn100i 62 1.2v -3 tqfp 100 ind 3.1k lfxp3e-4tn100i 62 1.2v -4 tqfp 100 ind 3.1k part number i/os voltage grade package pins temp. luts lfxp6e-3fn256i 188 1.2v -3 fpbga 256 ind 5.8k lfxp6e-4fn256i 188 1.2v -4 fpbga 256 ind 5.8k lfxp6e-3qn208i 142 1.2v -3 pqfp 208 ind 5.8k lfxp6e-4qn208i 142 1.2v -4 pqfp 208 ind 5.8k lfxp6e-3tn144i 100 1.2v -3 tqfp 144 ind 5.8k lfxp6e-4tn144i 100 1.2v -4 tqfp 144 ind 5.8k
5-12 ordering information lattice semiconductor latticexp family data sheet industrial (cont.) part number i/os voltage grade package pins temp. luts lfxp10e-3fn388i 244 1.2v -3 fpbga 388 ind 9.7k lfxp10e-4fn388i 244 1.2v -4 fpbga 388 ind 9.7k lfxp10e-3fn256i 188 1.2v -3 fpbga 256 ind 9.7k lfxp10e-4fn256i 188 1.2v -4 fpbga 256 ind 9.7k part number i/os voltage grade package pins temp. luts LFXP15e-3fn484i 300 1.2v -3 fpbga 484 ind 15.5k LFXP15e-4fn484i 300 1.2v -4 fpbga 484 ind 15.5k LFXP15e-3fn388i 268 1.2v -3 fpbga 388 ind 15.5k LFXP15e-4fn388i 268 1.2v -4 fpbga 388 ind 15.5k LFXP15e-3fn256i 188 1.2v -3 fpbga 256 ind 15.5k LFXP15e-4fn256i 188 1.2v -4 fpbga 256 ind 15.5k part number i/os voltage grade package pins temp. luts lfxp20e-3fn484i 340 1.2v -3 fpbga 484 ind 19.7k lfxp20e-4fn484i 340 1.2v -4 fpbga 484 ind 19.7k lfxp20e-3fn388i 268 1.2v -3 fpbga 388 ind 19.7k lfxp20e-4fn388i 268 1.2v -4 fpbga 388 ind 19.7k lfxp20e-3fn256i 188 1.2v -3 fpbga 256 ind 19.7k lfxp20e-4fn256i 188 1.2v -4 fpbga 256 ind 19.7k
november 2007 data sheet ds1001 ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1001 further information_01.3 for further information a variety of technical notes for the latticexp family are available on the lattice website at www .latticesemi.com . latticeecp/ec and latticexp sysio usage guide (tn1056) lattice isptracy usage guide (tn1054) latticeecp/ec and latticexp sysclock pll design and usage guide (tn1049) memory usage guide for latticeecp/ec and latticexp devices (tn1051) latticeecp/ec and xp ddr usage guide (tn1050) power estimation and management for latticeecp/ec and latticexp devices (tn1052) latticexp sysconfig usage guide (tn1082) for further information on interface standards refer to the following web sites: jedec standards (lvttl, lvcmos, sstl, hstl): www .jedec.org pci: www .pcisig.com latticexp family data sheet supplemental information
november 2007 data sheet ds1001 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 7-1 revision history date version section change summary february 2005 01.0 initial release. april 2005 01.1 architecture ebr memory support section updated with clari?ation. may 2005 01.2 introduction added transfr recon?uration to features section. architecture added transfr section. june 2005 01.3 pinout information added pinout information for lfxp3, lfxp6, LFXP15 and lfxp20. july 2005 02.0 introduction updated xp6, xp15 and xp20 ebr sram bits and block numbers. architecture updated per quadrant primary clock selection ?ure. added typical i/o behavior during power-up section. updated device con?uration section under con?uration and testing. dc and switching characteristics clari?d hot socketing speci?ation updated supply current (standby) table updated initialization supply current table added programming and erase flash supply current table added lvds emulation section. updated lvds25e output termination example ?ure and lvds25e dc conditions table. updated differential lvpecl diagram and lvpecl dc conditions table. deleted 5v tolerant input buffer section. updated rsds ?ure and rsds dc conditions table. updated sysconfig port timing speci?ations updated jtag port timing speci?ations. added flash download time table. pinout information updated signal descriptions table. updated logic signal connections dual function column. ordering information added lead-free ordering part numbers. july 2005 02.1 dc and switching characteristics clari?ation of flash programming junction temperature august 2005 02.2 introduction added sleep mode feature. architecture added sleep mode section. dc and switching characteristics added sleep mode supply current table added sleep mode timing section pinout information added sleepn and toe signal names, descriptions and footnotes. added sleepn and toe to pinout information and footnotes. added footnote 3 to logic signal connections tables for clari?ation on emulated lvds output. september 2005 03.0 architecture added clari?ation of pci clamp. added clari?ation to sleepn pin characteristics section. dc and switching characteristics dc characteristics, added footnote 4 for clari?ation. updated supply current (sleep mode), supply current (standby), initialization supply current, and programming and erase flash supply current typical numbers. latticexp family data sheet revision history
7-2 revision history lattice semiconductor latticexp family data sheet september 2005 (cont.) 03.0 (cont.) dc and switching characteristics (cont.) updated typical building block function performance timing numbers. updated external switching characteristics timing numbers. updated internal timing parameters. updated latticexp family timing adders. updated latticexp "c" sleep mode timing numbers. updated jtag port timing numbers. pinout information added clari?ation to sleepn and toe description. clari?ation of dedicated lvds outputs. supplemental information updated list of technical notes. september 2005 03.1 pinout information power supply and nc connections table corrected vccp1 pin number for 208 pqfp. december 2005 04.0 introduction moved data sheet from advance to final. architecture added clari?ation to typical i/o behavior during power-up section. dc and switching characteristics added clari?ation to recommended operating conditions. updated timing numbers. pinout information updated signal descriptions table. added clari?ation to differential i/o per bank. updated differential dedicated lvds output support. ordering information added 208 pqfp lead-free package and ordering part numbers. february 2006 04.1 pinout information corrected description of signal names vref1(x) and vref2(x). march 2006 04.2 dc and switching characteristics corrected condition for iil and iih. march 2006 04.3 dc and switching characteristics added clari?ation to recommended operating conditions for vccaux. april 2006 04.4 pinout information removed bank designator "5" from sleepn/toe ball function. may 2006 04.5 dc and switching characteristics added footnote 2 regarding threshold level for programn to syscon- fig port timing speci?ations table. june 2006 04.6 dc and switching characteristics corrected lvds25e output termination example. august 2006 04.7 architecture added clari?ation to typical i/o behavior during power-up section. added clari?ation to left and right sysio buffer pair section. dc and switching characteristics changes to lvds25e output termination example diagram. december 2006 04.8 architecture ebr asynchronous reset section added. february 2007 04.9 architecture updated ebr asynchronous reset section. july 2007 05.0 introduction updated latticexp family selection guide table. architecture updated typical i/o behavior during power-up text section. dc and switching characteristics updated sysio single-ended dc electrical characteristics table. split out lvcmos 1.2 by supply voltage. november 2007 05.1 dc and switching characteristics added jtag port timing waveforms diagram. pinout information added thermal management text section. supplemental information updated title list. date version section change summary

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